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Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 83件中 1~20件目  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
HWS, VLD 2019-02-27
13:55
Okinawa Okinawa Ken Seinen Kaikan Set-Pair Routing Algorithm with Selective Pin-Pair Connections
Kano Akagi, Shimpei Sato, Atsushi Takahashi (Tokyo Tech)
We propose a set-pair routing algorithm which efficiently generates a length matched routing pattern. In our algorithm, ... [more] VLD2018-99 HWS2018-62
pp.37-42
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2019-01-30
10:30
Kanagawa Raiosha, Hiyoshi Campus, Keio University On Delay Optimization for Improving General Synchronous Performance
Eijiro Sassa, Shimpei Sato, Atsushi Takahashi (Tokyo Tech)
 [more] VLD2018-72 CPSY2018-82 RECONF2018-46
pp.1-6
NC, MBE
(Joint)
2018-12-15
15:30
Aichi Nagoya Institute of Technology Proposal of Analysis Accuracy Improvement Method by Logistic Regression in Single Nucleotide Polymorphism Analysis Using Next-Generation Sequencer
Ginji Azuma (Kindai Univ.), Atsushi Takahashi (NCVC), Naoki Ohboshi (Kindai Univ.)
Single nucleotide polymorphisms are known to be related to phenotypes, and analysis is actively performed. However, the ... [more] NC2018-37
pp.51-55
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2018-12-07
14:10
Hiroshima Satellite Campus Hiroshima Process Variation-aware Model-based OPC using 0-1 Quadratic Programming
Rina Azuma, Yukihide Kohira (Univ. of Aizu), Tomomi Matsui, Atsushi Takahashi (Tokyo Tech), Chikaaki Kodama, Shigeki Nojima (TMC)
Due to continuous shrinking of Critical Dimensions (CD) of layout pattern in VLSI, advances of manufacturing process in ... [more] VLD2018-70 DC2018-56
pp.209-214
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-08
15:30
Kumamoto Kumamoto-Kenminkouryukan Parea A Study on Target Pin-Pairs Selection for Set-Pair Routing
Kano Akagi, Shimpei Sato, Atsushi Takahashi (Tokyo Tech.)
 [more] VLD2017-59 DC2017-65
pp.235-240
SIP, CAS, MSS, VLD 2017-06-20
15:30
Niigata Niigata University, Ikarashi Campus Evaluation of Trade-off between Performance and Area in a Variable Latency Arithmetic Circuit
Yuta Ukon, Shimpei Sato, Atsushi Takahashi (Tokyo Inst. of Tech.)
There are a lot of high load processing that is not required high accuracy at the data center. An approximate computing ... [more] CAS2017-23 VLD2017-26 SIP2017-47 MSS2017-23
pp.119-124
VLD, IPSJ-SLDM 2017-05-10
16:05
Fukuoka Kitakyushu International Conference Center [Invited Talk] Launch of IEEE CEDA All Japan Joint Chapter and Its Role
Atsushi Takahashi (Tokyo Tech)
IEEE the Council on Electronic Design Automation (CEDA) All Japan Joint Chapter (AJJC) was founded in 2014. In this manu... [more] VLD2017-3
pp.13-16
VLD 2017-03-02
10:30
Okinawa Okinawa Seinen Kaikan High-speed TPL Layout Decomposition Method based on Positive Semidefinite Relaxation using Polygon Clustering
Shohei Handa, Shimpei Sato, Atsushi Takahashi (Tokyo TECH)
 [more] VLD2016-111
pp.55-60
VLD 2017-03-02
11:20
Okinawa Okinawa Seinen Kaikan Efficient Local Pattern Modification Method using FM Algorithm in LELE Double Patterning
Atsushi Ogashira, Shimpei Sato, Atsushi Takahashi (Tokyo TECH)
In current semiconductor design, high quality and short time design is required.
In an advanced lithography technology... [more]
VLD2016-113
pp.67-72
VLD 2017-03-02
11:45
Okinawa Okinawa Seinen Kaikan Partial Route Modification Method to Realize Target Equi-length on Single Layer PCB Routing
Shun Sugihara, Shimpei Sato, Atsushi Takahashi (Tokyo Tech)
In printed circuit board, to meet requirements such as delay and noise,
routing of each net is necessary to achieve its... [more]
VLD2016-114
pp.73-78
CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] 2017-01-25
09:25
Kanagawa Hiyoshi Campus, Keio Univ. Investigation of the influence of input sequences on the calculation accuracy in an approximate operation using a typical circuit
Shimpei Sato, Yuta Ukon, Atsushi Takahashi (Tokyo TECH)
When variable latency for digital circuits are assumed, circuits can work with a small clock period that
has the possib... [more]
VLD2016-95 CPSY2016-131 RECONF2016-76
pp.165-170
MBE, NC
(Joint)
2016-03-22
10:55
Tokyo Tamagawa University Attempt of high frequency blocking in surface electrical stimulation
Atsushi Takahashi, Ryoko Futami (Fukushima Uni.)
Two experiments to develop a new selective nerve stimulation method were performed.
In the first experiment, we used tw... [more]
MBE2015-106
pp.17-20
VLD 2016-03-02
10:30
Okinawa Okinawa Seinen Kaikan Self-Aligned Quadruple Patterning-Aware Three-Color Grid Routing with Different Color Net
Toshiyuki Hongo, Atsushi Takahashi (Tokyo Tech)
Self-Aligned Quadruple Patterning (SAQP) is an important manufacturing technique for sub 14 nm technology node.
In this... [more]
VLD2015-135
pp.137-142
VLD 2016-03-02
13:50
Okinawa Okinawa Seinen Kaikan Acceleration of General Synchronous Circuits by Variable Latency Technique using Dynamic Timing-Error Detection
Hiroshi Nakatsuka, Atsushi Takahashi (Tokyo Tech)
General synchronous circuits are proposed as having taken the place of complete synchronous circuits and do not necessar... [more] VLD2015-140
pp.167-172
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-02
17:10
Nagasaki Nagasaki Kinro Fukushi Kaikan Effective Routing Pattern Generation with an Optimum Tertiary Routing Algorithm for Self-Aligned Quadruple Patterning
Takeshi Ihara, Atsushi Takahashi (Tokyo Tech)
Self-Aligned Quadruple Patterning (SAQP) is an important manufacturing technique for sub 14 nm technology node.
Althou... [more]
VLD2015-53 DC2015-49
pp.93-98
MSS, CAS, SIP, VLD 2015-06-17
16:20
Hokkaido Otaru University of Commerce [Panel Discussion] The Role of System and Signal Processing Subsociety -- Society Activity and Job Search --
Atsushi Takahashi (Tokyo Tech), Yoshihiro Kaneko (Gifu Univ.), Yusuke Matsunaga (Kyushu Univ.), Osamu Hoshuyama, Yuichi Nakamura (NEC)
The four technical committees of System and Signal Processing Subsociety have been holding joint workshop since 2010. We... [more] CAS2015-12 VLD2015-19 SIP2015-43 MSS2015-12
p.65
VLD, IPSJ-SLDM 2015-05-14
10:05
Fukuoka Kitakyushu International Conference Center NP-completeness of Routing Problem with Bend Constraint
Toshiyuki Hongo, Atsushi Takahashi (Tokyo Tech)
Self-Aligned Quadruple Patterning (SAQP) in which side-wall process is repeated twice is an important manufacturing tech... [more] VLD2015-3
pp.13-18
SDM 2015-03-02
13:05
Tokyo Kikai-Shinko-Kaikan Bldg [Invited Talk] Area dependence of thermal stability factor in perpendicular STT-MRAM analized by bi-directional data flipping model
Koji Tsunoda, Masaki Aoki, Hideyuki Noshiro, Yoshihisa Iba, Chikako Yoshida, Yuuichi Yamazaki, Atsushi Takahashi, Akiyoshi Hatada, Masaaki Nakabayashi, Toshihiro Sugii (LEAP)
We report a statistical analysis of the thermal stability factor (delta) for the top-pinned perpendicular magnetic tunne... [more] SDM2014-166
pp.23-28
VLD 2015-03-02
13:00
Okinawa Okinawa Seinen Kaikan A Fast Lithographic Mask Correction Algorithm
Ahmd Awad, Atsushi Takahashi (Tokyo Institute of Technology)
As technology nodes downscaling into sub-16 nm regime, the industry relies heavily on Optical Proximity
Correction (OP... [more]
VLD2014-153
pp.1-6
VLD 2015-03-02
13:25
Okinawa Okinawa Seinen Kaikan A cut-pattern reduction method for routing in Self-Aligned Double Patterning
Noriyuki Takahashi, Takeshi Ihara, Atsushi Takahashi (Tokyo Tech)
In Self-Aligned Double Patterning (SADP),
a routing method that generates a SADP friendly routing pattern efficiently
... [more]
VLD2014-154
pp.7-12
 83件中 1~20件目  /  [Next]  
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