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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 6 of 6  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
SITE, IPSJ-EIP 2022-06-10
12:50
Tokyo
(Primary: On-site, Secondary: Online)
HCD Ethics Guidelines Development
Shigeyoshi Iizuka (Kanagawa Univ.), Jun Iio (Chuo Univ.), Atsushi Hasegawa (Concent), Seiji Hayakawa (HCD YOROZU Consulting), Hiroshi Tsujioka (HCD-Net)
(To be available after the conference date) [more]
NLP, CAS 2017-10-06
13:50
Niigata Machinaka Campus Nagaoka An experimental investigation of forced synchronization in passive walking robot on periodically vibrating base
Atsushi Hasegawa, Tadashi Tsubone (Nagaoka Univ. Tech.) CAS2017-39 NLP2017-64
In this study, we experimentally verify synchronization phenomenon observed in a passive walking robot on periodically v... [more] CAS2017-39 NLP2017-64
pp.81-86
NLP 2017-03-14
15:20
Aomori Nebuta Museum Warasse Experimental verification of synchronization phenomenon observed in passive walking robots on a hung base
Atsushi Hasegawa, Tadashi Tsubone (Nagaoka Univ. Tech.) NLP2016-115
In this study, we experimentally verify synchronization phenomenon observed in passive walking robots on a hung base to ... [more] NLP2016-115
pp.53-56
ICD 2009-12-15
17:00
Shizuoka Shizuoka University (Hamamatsu) A 3D Processor Using Inductive-Coupling Inter-Chip Link -- 3D System Integration of a 90nm CMOS Processor and a 65nm CMOS SRAM --
Kiichi Niitsu (Keio Univ./JST), Yasuhisa Shimazaki (Keio Univ./Renesas Technology), Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga (Keio Univ.), Itaru Nonomura (Renesas Technology), Makoto Saen, Shigenobu Komatsu, Kenichi Osada, Naohiko Irie (Hitachi), Toshihiro Hattori, Atsushi Hasegawa (Renesas Technology), Tadahiro Kuroda (Keio Univ.) ICD2009-105
A 90nm CMOS processor is mounted face down on a package by C4 bump and a 65nm CMOS 1MB SRAM is glued on it face up. The ... [more] ICD2009-105
pp.163-168
ICD, IPSJ-ARC 2007-05-31
13:45
Kanagawa   Mutligrain Parallel Processing in SMP Execution Mode on a Multicore for Consumer Electronics
Masayoshi Mase, Daisuke Baba, Harumi Nagayama, Hiroaki Tano, Takeshi Masuura, Takamichi Miyamoto, Jun Shirako, Hirofumi Nakano, Keiji Kimura (Waseda Univ.), Tatsuya Kamei, Toshihiro Hattori, Atsushi Hasegawa (Renesas Technology), Masaki Ito, Makoto Satoh, Kunio Uchiyama (Hitachi Ltd.)
Currently, multicore processors are becoming ubiquitous in various computing domains, namely con-
sumer electronics suc... [more]
ICD2007-21
pp.25-30
ICD, IPSJ-ARC 2007-05-31
14:15
Kanagawa   A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption
Kiyoshi Hayase, Yutaka Yoshida, Tatsuya Kamei, Shinichi Shibahara, Osamu Nishii, Toshihiro Hattori, Atsushi Hasegawa (Renesas technology), Masashi Takada, Naohiko Irie, Kunio Uchiyama, Toshihiko Odaka (Hitachi Ltd.), Kiwamu Takada (Hitachi ULSI Systems Co. Ltd.), Keiji Kimura, Hironori Kasahara (Waseda Univ.) ICD2007-22
4320MIPS 4-processor SoC that provides with low power consumption and high performance was designed using 90nm process. ... [more] ICD2007-22
pp.31-35
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