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Committee Date Time Place Paper Title / Authors Abstract Paper #
(Joint) [detail]
Fukuoka Kyushu University [Invited Talk] A wafer-level system integration technology for heterogeneous devices with pseudo-SoC
Hiroshi Yamada, Yutaka Onozuka, Atsuko Iida, Kazuhiko Itaya, Hideyuki Funaki (Toshiba R&D Center) CPM2010-135 ICD2010-94
A wafer level system integration technology for heterogeneous devices has been developed by applying pseudo-SOC.
The ... [more]
CPM2010-135 ICD2010-94
CPM, ICD 2008-01-18
Tokyo Kikai-Shinko-Kaikan Bldg Study on Low Stress Condition of Pseudo-SOC Integration Using Stress Analysis
Yutaka Onozuka, Hiroshi Yamada, Atsuko Iida, Kazuhiko Itaya, Hideyuki Funaki (Toshiba R & D Center) CPM2007-141 ICD2007-152
The authors have proposed a pseudo-SOC (System on Chip) technology, forming redistribution global layer with semiconduct... [more] CPM2007-141 ICD2007-152
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