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Committee Date Time Place Paper Title / Authors Abstract Paper #
HWS, VLD 2019-02-27
13:05		 Okinawa Okinawa Ken Seinen Kaikan Wire Load Model for Power Consumption Evaluation of Via-Switch FPGA
Asuka Natsuhara, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2018-97 HWS2018-60		 In this report, we consider a wire load model for an FPGA using new nano-device called via-switch to allow power estimat... [more] VLD2018-97 HWS2018-60
pp.25-30
IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2018-01-19
11:05		 Kanagawa Raiosha, Hiyoshi Campus, Keio University A study on the power efficiency of via-switch oriented programmable logic 0-1-A-~A LUT
Asuka Natsuhara, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2017-80 CPSY2017-124 RECONF2017-68		 This paper quantitatively shows the superiority of 0-1-$A$-$overline{A}$ LUT to 0-1 LUT in terms of area, delay time and... [more] VLD2017-80 CPSY2017-124 RECONF2017-68
pp.107-112
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