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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2012-04-24 14:50 |
Iwate | Seion-so, Tsunagi Hot Spring (Iwate) | Device-Conscious Circuit Designs for 0.5-V High-Speed Nanoscale CMOS LSIs Akira Kotabe, Kiyoo Itoh, Riichiro Takemura, Ryuta Tsuchiya (Hitachi), Masashi Horiguchi (Renesas)  ICD2012-15 |
The feasibility of 0.5-V memory-rich nanoscale CMOS LSIs was studied. First, nanoscale fully-depleted MOSFETs (FD MOS) a... [more] | ICD2012-15 pp.79-84 |
| SDM, ICD | 2011-08-26 13:40 |
Toyama | Toyama kenminkaikan | Ultra low noise in-substrate-bitline sense amplifier for 4F2 DRAM array Yoshimitsu Yanagawa, Tomonori Sekiguchi, Akira Kotabe, Kazuo Ono, Riichiro Takemura (Hitachi) SDM2011-89 ICD2011-57 |
An in-substrate-bitline sense amplifier (SA) with an array-noise-gating (ANG) scheme for stable sensing operation in a 4... [more] | SDM2011-89 ICD2011-57 pp.93-97 |
| SDM, ICD | 2011-08-26 14:05 |
Toyama | Toyama kenminkaikan | Sense Amplifier with Current Control Switch for Small-sized 0.5-V Gigabit-DRAM Arrays Akira Kotabe, Yoshimitsu Yanagawa, Riichiro Takemura, Tomonori Sekiguchi, Kiyoo Itoh (Hitachi) SDM2011-90 ICD2011-58 |
[more] | SDM2011-90 ICD2011-58 pp.99-102 |
| ICD | 2011-04-19 14:00 |
Hyogo | Kobe University Takigawa Memorial Hall | 1-Tbyte/s 1-Gbit Multicore DRAM Architecture using 3-D Integration for High-throughput Computing Kazuo Ono, Yoshimitsu Yanagawa, Akira Kotabe, Tomonori Sekiguchi (Hitachi, CRL) ICD2011-15 |
A novel multicore DRAM architecture with an ultra high bandwidth and a large capacity is proposed for high throughput co... [more] | ICD2011-15 pp.81-86 |
| ICD, SDM | 2010-08-26 13:00 |
Hokkaido | Sapporo Center for Gender Equality | 1-Tbyte/s 1-Gbit 3-D DRAM Architecture for High Throughput Computing Yoshimitsu Yanagawa, Kazuo Ono, Akira Kotabe, Tomonori Sekiguchi (Hitachi) SDM2010-131 ICD2010-46 |
A novel DRAM architecture with an ultra high bandwidth is proposed for high throughput computing. The proposed architect... [more] | SDM2010-131 ICD2010-46 pp.39-44 |
| ICD | 2010-04-22 12:05 |
Kanagawa | Shonan Institute of Tech. | Low-VT CMOS Preamplifier for 0.5-V Gigabit-DRAM Arrays Akira Kotabe, Yoshimitsu Yanagawa, Satoru Akiyama, Tomonori Sekiguchi (Hitachi) ICD2010-6 |
A novel low-VT CMOS preamplifier was developed for low-power and high-speed gigabit DRAM arrays. The sensing time of the... [more] | ICD2010-6 pp.29-33 |
| ICD | 2009-04-13 13:30 |
Miyagi | Daikanso (Matsushima, Miyagi) | [Invited Talk]
Trend in Multi-Gigabit DRAM Technology and Low-Vt Small-Offset Gated Preamplifier for Sub-1-V Arrays Satoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura, Akira Kotabe, Kiyoo Itoh (Hitachi, Ltd.,) ICD2009-2 |
[more] | ICD2009-2 pp.7-12 |
| ICD | 2007-04-12 11:10 |
Oita | [Invited Talk]
A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current Akira Kotabe, Satoru Hanzawa (Hitachi), Naoki Kitai (Hitachi ULSI), Kenichi Osada, Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura (Hitachi), Masahiro Moniwa (Renesas), Takayuki Kawahara (Hitachi) ICD2007-5 |
An experimental 512-kB embedded Phase Change Memory (PCM) is developed in a 0.13-μm 1.5-V CMOS technology. Three circuit... [more] | ICD2007-5 pp.23-28 |
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| ICD, SDM | 2006-08-18 15:25 |
Hokkaido | Hokkaido University | Impact of Random Telegraph Signals on Scaling of Multilevel Flash Memories Hideaki Kurata, Kazuo Otsuga, Akira Kotabe, Shinya Kajiyama, Taro Osabe, Yoshitaka Sasago (Hitachi), Shunichi Narumi, Kenji Tokami, Shiro Kamohara, Osamu Tsuchiya (Renesas) |
This paper describes for the first time the observation of the threshold voltage (Vth) fluctuation due to random telegra... [more] | SDM2006-153 ICD2006-107 pp.161-166 |
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