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Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM, ICD 2015-08-24
10:55		 Kumamoto Kumamoto City [Invited Talk] Implementation of TFET Spice Model for Ultra-Low Power Circuit Analysis
Chika Tanaka, Akira Hokazono, Kanna Adachi, Masakazu Goto, Yoshiyuki Kondo, Emiko Sugizaki, Motohiko Fujimatsu, Hiroyuki Hara, Shinji Miyano, Keiichi Kushida, Shigeru Kawanaka (Toshiba) SDM2015-59 ICD2015-28		  [more] SDM2015-59 ICD2015-28
pp.11-13
SDM, ICD 2013-08-01
09:50		 Ishikawa Kanazawa University Scaling Strategy for Low Power RF Applications with Multi Gate Oxide Dual Work function (DWF) MOSFETs Utilizing Self-Aligned Integration Scheme
Toshitaka Miyata, Shigeru Kawanaka, Akira Hokazono, Tatsuya Ohguro, Yoshiaki Toyoshima (TOSHIBA) SDM2013-67 ICD2013-49		 Dual Work Function (DWF)-MOSFET of 100 nm gate length device with self-aligned integration scheme was demonstrated utili... [more] SDM2013-67 ICD2013-49
pp.13-18
SDM, ICD 2011-08-25
10:50		 Toyama Toyama kenminkaikan Plasma Doping and Laser Spike Annealing Technique for Steep SDE Formation in nano-scale MOSFET
Emiko Sugizaki, Toshitaka Miyata, Yasunori Oshima, Akira Hokazono, Kanna Adachi, Kiyotaka Miyano, Hideji Tsujii, Shigeru Kawanaka, Satoshi Inaba, Takaharu Itani, Toshihiko Iinuma, Yoshiaki Toyoshima (Toshiba) SDM2011-75 ICD2011-43		 The importance of impurity profile design for Source/Drain Extension (SDE) is widely recognized for deeply scaled MOSFET... [more] SDM2011-75 ICD2011-43
pp.23-27
SDM, VLD 2007-10-30
14:10		 Tokyo Kikai-Shinko-Kaikan Bldg. Study of Parasitic Resistance Behavior and Its Extraction Method on Deeply Scaled MOSFETs
Hideji Tsujii, Akira Hokazono, Makoto Fujiwara, Shigeru Kawanaka, Atsushi Azuma, Nobutoshi Aoki, Yoshiaki Toyoshima (Toshiba) VLD2007-56 SDM2007-200		  [more] VLD2007-56 SDM2007-200
pp.27-32
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