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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
IA, SITE, IPSJ-IOT [detail] |
2013-03-14 16:25 |
Nara |
Todaiji Total Cultural Center |
A Flood Hazard Model Based on Damage Situations Kei Hiroi (Keio Univ.), Yuzo Taenaka (Univ. of Tokyo), Kanae Matsui (Keio Univ.), Hideya Ochiai (Univ. of Tokyo), Hitoshi Yokoyama (Tokanken), Hideki Sunahara (Keio Univ.) SITE2012-58 IA2012-96 |
People in the disaster risk area needs disaster information such as river levels for reduction of disaster damages. Howe... [more] |
SITE2012-58 IA2012-96 pp.123-126 |
ISEC, LOIS |
2012-11-21 14:15 |
Shizuoka |
Shizuoka City Industry-University Exchange Center |
How to Extract AES Key from Smart Card by Fault Injection Attack Using Electromaginetic Irradiataion Yuu Tsuchiya, Takeshi Kishikawa, Shohei Saito, Tsuyoshi Toyama (YNU), Akihiko Sasaki (MORITA TECH), Akashi Satoh (VDEC, Univ. Tokyo), Tsutomu Matsumoto (YNU) ISEC2012-57 LOIS2012-32 |
Fault injection attack, inducing partial fault in a cryptographic module and extracting the inside key, has been conside... [more] |
ISEC2012-57 LOIS2012-32 pp.1-8 |
ICD, ITE-IST |
2011-07-22 09:50 |
Hiroshima |
Hiroshima Institute of Technology |
On-Chip Resonant Supply Noise Reduction Using Active Decoupling Capacitors Jinmyoung Kim (Tokyo Univ.), Toru Nakura (VDEC), Hidehiro Takata, Koichiro Ishibashi (Renesas Electronics), Makoto Ikeda, Kunihiro Asada (VDEC) ICD2011-27 |
[more] |
ICD2011-27 pp.69-72 |
ICD, SDM |
2010-08-26 09:10 |
Hokkaido |
Sapporo Center for Gender Equality |
On-Chip Supply Resonance Noise Reduction Method for Multi-IP Cores utilizing Parasitic Capacitance of Sleep Blocks Jinmyoung Kim, Toru Nakura (Univ. of Tokyo.), Hidehiro Takata, Koichiro Ishibashi (Renesas Electronics), Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo.) SDM2010-124 ICD2010-39 |
This paper proposes an on-chip supply resonance noise reduction method for multi-IP cores utilizing parasitic capacitanc... [more] |
SDM2010-124 ICD2010-39 pp.1-4 |
DC, CPSY, IPSJ-SLDM, IPSJ-EMB |
2008-03-28 10:30 |
Kagoshima |
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A technique of automatic input pattern generation for system-level design descriptions by concrete and symbolic simulations Yoshihisa Kojima, Tasuku Nishihara, Takeshi Matsumoto (Univ. of Tokyo), Masahiro Fujita (VDEC, Univ of Tokyo) DC2007-106 CPSY2007-102 |
As the VLSI systems grow larger and more complicated, it becomes more difficult to manually prepare the input patterns o... [more] |
DC2007-106 CPSY2007-102 pp.133-138 |
VLD, ICD |
2008-03-05 13:00 |
Okinawa |
TiRuRu |
Automatic synthesis and verification of practical protocol transducer based on product graph exploration Yuji Ishikawa (Univ. of Tokyo), Satoshi Komatsu, Masahiro Fujita (VDEC, Univ. of Tokyo) VLD2007-137 ICD2007-160 |
[more] |
VLD2007-137 ICD2007-160 pp.1-6 |
ICD, ITE-IST |
2007-07-27 10:45 |
Hyogo |
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Electrical Characteristics of MAGFET With On-Chip Coil Hirokazu Hashimoto (The Univ. of Tokyo), Makoto Ikeda, Kunihiro Asada (VDEC) ICD2007-59 |
MAGFET ( Magnetic MOS Field-Effect Transistor ) is one of the magnetic sensors, which is capable of sensing a magnetic f... [more] |
ICD2007-59 pp.129-134 |
ICD, CPM |
2007-01-18 09:25 |
Tokyo |
Kika-Shinko-Kaikan Bldg. |
Study on Active Substrate Noise Cancelling Technique using Power Line di/dt Detector Taisuke Kazama (Univ. of Tokyo), Makoto Ikeda, Kunihiro Asada (VDEC) |
[more] |
CPM2006-130 ICD2006-172 pp.7-12 |
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