Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
ICD, ITE-IST |
2013-07-04 09:30 |
Hokkaido |
San Refre Hakodate |
93% Power Reduction by Automatic Self Power Gating (ASPG) and Multistage Inverter for Negative Resistance (MINR) in 0.7V, 9.2uW, 39MHz Crystal Oscillator Shunta Iguchi (Univ. of Tokyo), Akira Saito (STARC), Yunfei Zheng (Univ. of Tokyo), Kazunori Watanabe (STARC), Takayasu Sakurai, Makoto Takamiya (Univ. of Tokyo) ICD2013-24 |
In order to reduce the power consumption of a crystal oscillator (XO), an automatic self power gating (ASPG) and a multi... [more] |
ICD2013-24 pp.1-6 |
ICD, ITE-IST |
2013-07-04 10:20 |
Hokkaido |
San Refre Hakodate |
Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near-Threshold Logic Circuits Hiroshi Fuketa (Univ. of Tokyo), Masahiro Nomura (STARC), Makoto Takamiya, Takayasu Sakurai (Univ. of Tokyo) ICD2013-26 |
In order to eliminate the limitation of a narrow frequency range of conventional resonant clocking, intermittent resonan... [more] |
ICD2013-26 pp.13-18 |
ICD |
2013-04-12 14:45 |
Ibaraki |
Advanced Industrial Science and Technology (AIST) |
[Invited Lecture]
A 13.8pJ/Access/Mbit SRAM with Charge Collector Circuits for Effective Use of Non-Selected Bit Line Charges Shinichi Moriwaki, Yasue Yamamoto, Toshikazu Suzuki (STARC), Atsushi Kawasumi (Toshiba), Shinji Miyano, Hirofumi Shinohara (STARC), Takayasu Sakurai (Univ. Tokyo) ICD2013-20 |
1Mb SRAM with charge collector circuits for effective use of non-selected bit line charges has been fabricated in 40nm t... [more] |
ICD2013-20 pp.103-108 |
MW |
2013-03-07 14:20 |
Hiroshima |
Hiroshima Univ. |
[Invited Talk]
A Sub-50uW, 0.5V, 315MHz Transceiver for Wireless Sensor Networks Makoto Takamiya (Univ. of Tokyo), Akira Saito (STARC), Shunta Iguchi, Kentaro Honda, Yunfei Zheng (Univ. of Tokyo), Kazunori Watanabe (STARC), Takayasu Sakurai (Univ. of Tokyo) MW2012-177 |
[more] |
MW2012-177 pp.97-102 |
ICD |
2012-12-17 15:55 |
Tokyo |
Tokyo Tech Front |
[Poster Presentation]
Near Threshold Voltage Word-Line Voltage Injection Scheme for Self-Convergence of Threshold Voltage Variation in Local Electron Injected Asymmetric Pass Gate Transistor 6T-SRAM Daisuke Kobayashi, Kousuke Miyaji (Chuo Univ.), Shinji Miyano (STARC), Ken Takeuchi (Chuo Univ.) ICD2012-94 |
In order to repair the reduction of read margin by the variation of threshold voltage VTH in 6T-SRAM, a unique scheme th... [more] |
ICD2012-94 p.31 |
ICD |
2012-12-18 14:20 |
Tokyo |
Tokyo Tech Front |
High Efficiency 315MHz Transmitter with Dual Supply Voltage Scheme Shunta Iguchi (Univ. of Tokyo), Akira Saito, Kazunori Watanabe (STARC), Takayasu Sakurai, Makoto Takamiya (Univ. of Tokyo) ICD2012-119 |
Dual power supply voltage (VDD) scheme is proposed to increase the efficiency of a power amplifier (PA) with small outpu... [more] |
ICD2012-119 pp.121-126 |
MW (Workshop) |
2012-08-08 - 2012-08-10 |
Overseas |
Chulalongkorn University, Bangkok, Thailand |
150GHz CMOS ASK Transmitter Kosuke Katayama, Mizuki Motoyoshi, Kyoya Takano (Hiroshima Univ.), Naoko Ono (Toshiba Corp.), Minoru Fujishima (Hiroshima Univ.) |
In this paper we propose a 150GHz CMOS ASK transmitter that provides the highest ever reported carrier frequency for CMO... [more] |
|
ICD, SDM |
2012-08-02 09:35 |
Hokkaido |
Sapporo Center for Gender Equality, Sapporo, Hokkaido |
A 40-nm 256-Kb Sub-10 pJ/Access 8T SRAM with Read Bitline Amplitude Limiting (RBAL) Scheme Shusuke Yoshimoto, Masaharu Terada, Yohei Umeki, Shunsuke Okumura (Kobe Univ.), Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano (STARC), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) SDM2012-64 ICD2012-32 |
[more] |
SDM2012-64 ICD2012-32 pp.7-12 |
ICD, SDM |
2012-08-02 10:00 |
Hokkaido |
Sapporo Center for Gender Equality, Sapporo, Hokkaido |
Self-Improvement of Cell Stability in SRAM by Post Fabrication Technique Anil Kumar, Takuya Saraya (Univ. of Tokyo), Shinji Miyano (STARC), Toshiro Hiramoto (Univ. of Tokyo) SDM2012-65 ICD2012-33 |
The post fabrication technique for self-improvement of SRAM cell stability is validated by experiment using 1k DMA SRAM ... [more] |
SDM2012-65 ICD2012-33 pp.13-16 |
ICD, SDM |
2012-08-02 11:25 |
Hokkaido |
Sapporo Center for Gender Equality, Sapporo, Hokkaido |
[Invited Talk]
Low Energy Dissipation Circuits with 0.5V Operation Voltage and Applications Hirofumi Shinohara (STARC) SDM2012-67 ICD2012-35 |
Extremely low voltage operation down to nearly or less than 0.5V has been gathering attention as a fundamental way to re... [more] |
SDM2012-67 ICD2012-35 pp.23-28 |
ICD, SDM |
2012-08-03 13:35 |
Hokkaido |
Sapporo Center for Gender Equality, Sapporo, Hokkaido |
0.45-V Input Higher Than 90% Efficiency Buck Converter with On-Chip Gate Boost Xin Zhang, Po-Hung Chen (Univ. of Tokyo), Yoshikatsu Ryu (STARC), Koichi Ishida (Univ. of Tokyo), Yasuyuki Okuma, Kazunori Watanabe (STARC), Takayasu Sakurai, Makoto Takamiya (Univ. of Tokyo) SDM2012-83 ICD2012-51 |
[more] |
SDM2012-83 ICD2012-51 pp.111-114 |
ICD, SDM |
2012-08-03 15:55 |
Hokkaido |
Sapporo Center for Gender Equality, Sapporo, Hokkaido |
An All 0.5V, 1Mbps, 315MHz OOK Transceiver with 38uW Carrier-Frequency-Free Intermittent Sampling Receiver and 52uW Class-F Transmitter in 40-nm CMOS Shunta Iguchi (Univ. of Tokyo), Akira Saito (STARC), Kentaro Honda, Yunfei Zheng (Univ. of Tokyo), Kazunori Watanabe (STARC), Takayasu Sakurai, Makoto Takamiya (Univ. of Tokyo) SDM2012-87 ICD2012-55 |
[more] |
SDM2012-87 ICD2012-55 pp.133-138 |
SDM, ED (Workshop) |
2012-06-29 12:00 |
Okinawa |
Okinawa Seinen-kaikan |
Reliability Measurement of PFETs under Post Fabrication Self-Improvement Scheme for SRAM Nurul Ezaila Alias, Anil Kumar, Takuya Saraya (Univ. of Tokyo), Shinji Miyano (STARC), Toshiro Hiramoto (Univ. of Tokyo) |
The negative bias temperature instability (NBTI) reliability of PFETs is measured under the post fabrication SRAM self-i... [more] |
|
ICD |
2012-04-24 13:00 |
Iwate |
Seion-so, Tsunagi Hot Spring (Iwate) |
[Invited Talk]
57% Faster Read, 31% Lower Read Energy, 256-Times Faster Injection 6T-SRAM with a Carrier-Injection Scheme to Pinpoint and Repair Disturb Fails Kousuke Miyaji (Univ. of Tokyo), Toshikazu Suzuki (Panasonic), Shinji Miyano (STARC), Ken Takeuchi (Univ. of Tokyo) ICD2012-12 |
[more] |
ICD2012-12 pp.61-66 |
ICD |
2012-04-24 13:50 |
Iwate |
Seion-so, Tsunagi Hot Spring (Iwate) |
0.4V SRAM with Bit Line Swing Suppression Charge Share Hierarchical Bit Line Scheme Shinichi Moriwaki, Atsushi Kawasumi (STARC), Toshikazu Suzuki (Panasonic), Yasue Yamamoto, Shinji Miyano, Hirofumi Shinohara (STARC), Takayasu Sakurai (Univ. of Tokyo) ICD2012-13 |
[more] |
ICD2012-13 pp.67-71 |
ICD |
2012-04-24 14:15 |
Iwate |
Seion-so, Tsunagi Hot Spring (Iwate) |
A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura (Kobe Univ.), Toshikazu Suzuki, Shinji Miyano (STARC), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2012-14 |
This paper presents a novel disturb mitigation scheme which achieves low-power and low-voltage operation for a deep sub-... [more] |
ICD2012-14 pp.73-78 |
SDM, ICD |
2011-08-26 16:05 |
Toyama |
Toyama kenminkaikan |
Reduction of Minimum Operating Voltage (VDDmin) of CMOS Logic Circuits with Post-Fabrication Automatically Selective Charge Injection Kentaro Honda, Katsuyuki Ikeuchi (Univ. of Tokyo), Masahiro Nomura (STARC), Makoto Takamiya, Takayasu Sakurai (Univ. of Tokyo) SDM2011-94 ICD2011-62 |
[more] |
SDM2011-94 ICD2011-62 pp.121-126 |
SDM, ICD |
2011-08-26 16:30 |
Toyama |
Toyama kenminkaikan |
Energy Efficiency Increase of Integer Unit Enabled by Contention-less Flip-Flops (CLFF) and Separated Supply Voltage between Flip-Flops and Combinational Logics Hiroshi Fuketa (Univ. of Tokyo), Koji Hirairi (STARC), Tadashi Yasufuku, Makoto Takamiya (Univ. of Tokyo), Masahiro Nomura, Hirofumi Shinohara (STARC), Takayasu Sakurai (Univ. of Tokyo) SDM2011-95 ICD2011-63 |
[more] |
SDM2011-95 ICD2011-63 pp.127-132 |
ICD, ITE-IST |
2011-07-22 16:10 |
Hiroshima |
Hiroshima Institute of Technology |
An 0.5V Transceiver in 65nm CMOS for High-Speed Wireless Proximity Interface Takeshi Matsubara (Keio Univ.), Isamu Hayashi (STARC), Abul Hasan Johari, Satoshi Kumaki, Kaoru Kohira, Tadahiro Kuroda, Hiroki Ishikuro (Keio Univ.) ICD2011-36 |
This paper presents a pulse-based inductive-coupling transceiver in 65nm CMOS for High-speed wireless proximity communic... [more] |
ICD2011-36 pp.119-123 |
ICD |
2011-04-19 11:20 |
Hyogo |
Kobe University Takigawa Memorial Hall |
0.5-V, 5.5-nsec Access Time, Bulk-CMOS 8T SRAM with Suspended Bit-Line Read Scheme Toshikazu Suzuki, Shinichi Moriwaki, Atsushi Kawasumi, Shinji Miyano, Hirofumi Shinohara (STARC) ICD2011-12 |
A low-voltage high-speed bulk-CMOS 8T SRAM is proposed. A novel 8-transistor (8T) memory cell with a complementary read ... [more] |
ICD2011-12 pp.65-70 |