IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 32  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
MW 2010-03-05
15:50
Kyoto Ryukoku Univ. A PLL Synthesizer Composed of Parallel Dual Modulus Prescaler with a step size of 0.5
Hideyuki Nakamizo, Kenichi Tajima, Ryoji Hayashi (Mitsubishi Electric Corp.), Toshiya Uozumi (Renesas Technology Corp.) MW2009-209
By reducing the step size of the programmable frequency divider in Fractional-N PLL from 1 to 0.5, the phase noise contr... [more] MW2009-209
pp.175-178
IPSJ-SLDM, VLD, CPSY, RECONF [detail] 2010-01-27
13:30
Kanagawa Keio Univ (Hiyoshi Campus) A Packet Classifier Using a Parallel Branching Program Machine
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.), Yoshifumi Kawamura (Renesas Tech Corp.) VLD2009-92 CPSY2009-74 RECONF2009-77
A branching program machine~(BM) is a special-purpose processor that
uses only two kinds of instructions: Branch and ... [more]
VLD2009-92 CPSY2009-74 RECONF2009-77
pp.143-148
ICD 2009-12-14
10:50
Shizuoka Shizuoka University (Hamamatsu) [Invited Talk] Experimental Evaluation Technique for Power Supply Noise and Logical Operation Failure
Mitsuya Fukazawa (Renesas Technology Corp.), Makoto Nagata (Kobe Univ.) ICD2009-77
Logical operations in CMOS digital integration are highly prone to fail as the amount of power supply (PS) drop approach... [more] ICD2009-77
pp.7-12
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2009-12-03
15:20
Kochi Kochi City Culture-Plaza A Virus Scanning Engine Using a Parallel Sieve Method and the MPU
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.), Yoshifumi Kawamura (Renesas Technology Corp.) RECONF2009-45
In this paper, we show a new architecture for the virus scanning machine,
which is different from that of the intrusi... [more]
RECONF2009-45
pp.25-30
ICD 2009-04-14
10:40
Miyagi Daikanso (Matsushima, Miyagi) A 0.56-V 128kb 10T SRAM Using Column Line Assist (CLA) Scheme
Shusuke Yoshimoto, Yusuke Iguchi, Shunsuke Okumura, Hidehiro Fujiwara, Hiroki Noguchi (Kobe Univ.), Koji Nii (Renesas Technology Corp.), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2009-6
We present a small-area 10T SRAM cell without half selection problem. As well, the proposed 10T cell achieves a faster a... [more] ICD2009-6
pp.27-32
ICD 2008-04-18
10:25
Tokyo   [Invited Talk] *
Shinji Kawai, Akira Hosogane, Shigehiro Kuge, Toshihiro Abe, Kohei Hashimoto, Tsukasa Oishi, Naoki Tsuji, Kiyohiko Sakakibara, Kenji Noguchi (Renesas) ICD2008-9
This paper describe an 8kB EEPROM-Emulation DataFLASH (E2FLASH) that replaces on-board EEPROM using dual-channel NOR-typ... [more] ICD2008-9
pp.45-50
SDM 2008-03-14
15:25
Tokyo Kikai-Shinko-Kaikan Bldg. Through-silicon Via Interconnection for 3D Integration Using Room-temperature Bonding
Naotaka Tanaka, Yasuhiro Yoshimura, Michihiro Kawashita (Hitachi), Toshihide Uematsu, Takahiro Naitoh, Takashi Akazawa (Renesas) SDM2007-277
One approach to 3D technology is chip stacking using through-silicon vias (TSVs). Interconnects in a 3D assembly are pot... [more] SDM2007-277
pp.21-26
ED, MW 2008-01-17
09:45
Tokyo Kikai-Shinko-Kaikan Bldg. Examination of dual band CMOS RF power amplifier circuit
Jun Kikuchi (Gunma Univ.), Hisayasu Sato (Renesas Technology Corporation), Noboru Ishihara (Gunma Univ.) ED2007-214 MW2007-145
Dual-band CMOS RF power amplifier circuit design techniques have been studied. In CMOS power amplifier design with low p... [more] ED2007-214 MW2007-145
pp.45-50
ED, MW 2008-01-17
10:10
Tokyo Kikai-Shinko-Kaikan Bldg. Wide-Band BPSK CMOS Demodulator Circuit
Yasuyuki Arai, Jun Kikuchi, Ryuichi Ujiie, Kenichi Shibata (Gunma Univ.), Tetuya Hirama, Hisayasu Sato (Renesas Technology), Noboru Ishihara (Gunma Univ.) ED2007-215 MW2007-146
In recent LSI systems, the wiring connections between the LSI and the LSI or the board and the board have become high de... [more] ED2007-215 MW2007-146
pp.51-56
IN 2007-12-13
16:15
Hiroshima Hiroshima City University Efficient Management of Access Control List by Combining Prefix Expansion and Range Matching Devices
Haesung Hwang (Osaka Univ.), Koji Yamamoto (Renesas Technology), Shingo Ata (Osaka City Uni.), Kazunari Inoue (Renesas Technology), Masayuki Murata (Osaka Univ.) IN2007-105
TCAM (Ternary Content Addressable Memory) is a special type of memory used in routers in order to achieve high speed pac... [more] IN2007-105
pp.37-42
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]
2007-11-22
15:45
Fukuoka Kitakyushu International Conference Center Memory Assignment Method Considering Orders of Operands for Massively Parallel Fine-grained SIMD Processor
Akira Kobashi, Ittetsu Taniguchi, Hiroaki Tanaka, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.), Kiyoshi Nakata (Renesas) VLD2007-104 DC2007-59
In recent years, spread of data intensive multimedia applications equires high-performance in embedded systems.
Massiv... [more]
VLD2007-104 DC2007-59
pp.91-96
SDM, R, ED 2007-11-16
16:10
Osaka   A New TDDB Degradation Model Based on Cu Ion Drift in Cu Interconnect Dielectrics
Naohito Suzumura, Shigehisa Yamamoto, , , Junko Komori, (Renesas Technology Corp.) R2007-53 ED2007-186 SDM2007-221
A new physical model of Time-Dependent Dielectric Breakdown (TDDB) in Cu interconnect dielectrics is proposed. TDDB occu... [more] R2007-53 ED2007-186 SDM2007-221
pp.39-44
SDM, VLD 2007-10-30
13:45
Tokyo Kikai-Shinko-Kaikan Bldg. Electro-Thermal Compact Model for Reset Operation of Phase Change Memories
Atsushi Sakai, Kenichiro Sonoda, Masahiro Moniwa, Kiyoshi Ishikawa, Osamu Tsuchiya, Yasuo Inoue (Renesas Technology Corp.) VLD2007-55 SDM2007-199
A three-dimensional (3D) electro-thermal compact model for the reset operation of a phase change memory (PCM) cell is pr... [more] VLD2007-55 SDM2007-199
pp.23-26
SDM, VLD 2007-10-30
15:00
Tokyo Kikai-Shinko-Kaikan Bldg. Impact of Shear Strain and Quantum Confinement on <110> Channel nMOSFET with High-Stress CESL
Hiroyuki Takashino, Takeshi Okagaki, Tetsuya Uchida, Takashi Hayashi, Motoaki Tanizawa, Eiji Tsukuda, Katsumi Eikyu, Shoji Wakahara, Kiyoshi Ishikawa, Osamu Tsuchiya, Yasuo Inoue (Renesas Technology Corp.) VLD2007-57 SDM2007-201
Numerical study in conjunction with comprehensive bending
experiments has demonstrated that \orientation{100}-Si has th... [more]
VLD2007-57 SDM2007-201
pp.33-36
CPSY 2007-10-25
13:00
Kumamoto Kumamoto University The application of the massively parallel processor based on the matrix architecture
Katsuya Mizumoto, Hiroyuki Yamasaki, Hideyuki Noda, Tetsushi Tanizaki, Takayuki Gyohten, Masami Nakajima, Motoki Higashida, Yoshihiro Okuno, Kazutami Arimoto (Renesas) CPSY2007-24
We have developed programmable matrix-processor "MX-1". The MX-1 consists of MX-Core and a control CPU. The MX-Core is a... [more] CPSY2007-24
pp.1-5
CPSY 2007-10-25
15:10
Kumamoto Kumamoto University Acceleration of Multimedia Data Processing with CAM-Enhanced Massive-Parallel SIMD Matrix Processor
Takeshi Kumaki, Masakatsu Ishizaki, Masaharu Tagami, Tetsushi Koide, Hans Juergen Mattausch (Hiroshima Univ.), Takayuki Gyohten, Hideyuki Noda, Yasuto Kuroda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito (Renesas Technology) CPSY2007-27
A multimedia processor requires four capabilities, fast processing, small area size, low power consumption and programma... [more] CPSY2007-27
pp.19-24
ICD, SDM 2007-08-23
09:20
Hokkaido Kitami Institute of Technology Evaluation of Heterogeneous Multicore Architecture with AAC-LC Stereo Encoding
Hiroaki Shikano (Hitachi/./Waseda Univ.), Masaki Ito, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Masafumi Onouchi, Kunio Uchiyama (Hitachi), Toshihiko Odaka (Hitachi/./Waseda Univ.), Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta (Renesas Technology), Yasutaka Wada, Keiji Kimura, Hironori Kasahara (Waseda Univ.) SDM2007-143 ICD2007-71
This paper describes a heterogeneous multi-core processor (HMCP) architecture which integrates general purpose processor... [more] SDM2007-143 ICD2007-71
pp.11-16
SR 2007-07-27
16:05
Kanagawa   A Downsized Moving-Average-Type Sampling filter
Nao Hamada, Ryoji Hayashi (Mitsubishi Electric Corp.), Tomohiro Sano, Hisayasu Sato (Renesas Technology Corp.) SR2007-43
This paper proposes two novel techniques to reduce the number of capacitors in moving-average-type (MAT) sampling filter... [more] SR2007-43
pp.145-150
VLD, IPSJ-SLDM 2007-05-10
13:30
Kyoto Kyodai Kaikan Memory Assignment Method for Matrix Processing Array
Akira Kobashi, Ittetsu Taniguchi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.), Kiyoshi Nakata (Renesas) VLD2007-1
MTA (MaTrix processing Array), which is developed by Renesas Technology Corp., can achieve high performance for digital ... [more] VLD2007-1
pp.1-6
ICD 2007-04-12
10:00
Oita   A high-density 1T-4MTJ MRAM with Self-Reference Sensing Scheme
Yasumitsu Murai, Hiroaki Tanizaki (Renesas Design), Takaharu Tsuji, Jun Otani, Yuichiro Yamaguchi, Haruo Furuta, Shuichi Ueno, Tsukasa Oishi, Masanori Hayashikoshi, Hideto Hidaka (Renesas) ICD2007-3
A high-density memory cell named 1-Transistor 4-Magnetic Tunnel Junction (1T-4MTJ) has been proposed for Magnetic Random... [more] ICD2007-3
pp.13-16
 Results 1 - 20 of 32  /  [Next]  
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan