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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 97  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, IPSJ-SLDM 2010-05-20
10:00
Fukuoka Kitakyushu International Conference Center 3D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link
Makoto Saen, Kenichi Osada, Yasuyuki Okuma (Hitachi), Yasuhisa Shimazaki (Keio Univ./Renesas Technology), Itaru Nonomura (Renesas Technology), Kiichi Niitsu, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Tadahiro Kuroda (Keio Univ.) VLD2010-5
This paper describes a three-dimensional (3D) system integration of a fully functional processor chip and two memory chi... [more] VLD2010-5
pp.43-47
ICD 2010-04-22
11:15
Kanagawa Shonan Institute of Tech. A 40-nm Low-power SRAM with Multi-stage Replica-Bitline Scheme for Reducing Timing Variation
Shigenobu Komatsu, Masanao Yamaoka (HITACHI), Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki (Renesas Technology Corp.), Kenichi Osada (HITACHI) ICD2010-4
A multi-stage replica bitline scheme for reducing access time by suppressing enable timing variation of a sense amplifie... [more] ICD2010-4
pp.17-21
MW 2010-03-05
15:50
Kyoto Ryukoku Univ. A PLL Synthesizer Composed of Parallel Dual Modulus Prescaler with a step size of 0.5
Hideyuki Nakamizo, Kenichi Tajima, Ryoji Hayashi (Mitsubishi Electric Corp.), Toshiya Uozumi (Renesas Technology Corp.) MW2009-209
By reducing the step size of the programmable frequency divider in Fractional-N PLL from 1 to 0.5, the phase noise contr... [more] MW2009-209
pp.175-178
SDM 2010-02-05
13:00
Tokyo Kikai-Shinko-Kaikan Bldg. Advanced Direct-CMP Process for Porous Low-k Thin Film
Hayato Korogi (Panasonic), Hiroyuki Chibahara (Renesas), S. Suzuki, M. Tsutsue (Panasonic), K. Seo (Panasonic Semiconductor Engineering), Y. Oka, K. Goto, M. Akazaw, Hiroshi Miyatake (Renesas), S. Matsumoto, T. Ueda (Panasonic) SDM2009-185
In order to reduce the effective dielectric constant (keff) for the 32 nm technology node and beyond, Direct-CMP of a po... [more] SDM2009-185
pp.19-23
SDM 2010-02-05
14:30
Tokyo Kikai-Shinko-Kaikan Bldg. Performance of Cu Dual-Damascene Interconnects Using a Thin Ti-Based Self-Formed Barrier Layer for 28-nm Node and Beyond
K. Ohmori, K. Mori, K. Maekawa (Renesas), Kazuyuki Kohama, Kazuhiro Ito (Kyoto Univ.), T. Ohnishi, M. Mizuno (KOBE STEEL), K. Asai (Renesas), M. Murakami (Ritsumeikan Trust), Hiroshi Miyatake (Renesas) SDM2009-188
With continuous shrinkage of advanced ULSIs, the impact of line resistance on the devices has become more and more serio... [more] SDM2009-188
pp.37-41
ICD 2009-12-14
10:50
Shizuoka Shizuoka University (Hamamatsu) [Invited Talk] Experimental Evaluation Technique for Power Supply Noise and Logical Operation Failure
Mitsuya Fukazawa (Renesas Technology Corp.), Makoto Nagata (Kobe Univ.) ICD2009-77
Logical operations in CMOS digital integration are highly prone to fail as the amount of power supply (PS) drop approach... [more] ICD2009-77
pp.7-12
ICD 2009-12-15
17:00
Shizuoka Shizuoka University (Hamamatsu) A 3D Processor Using Inductive-Coupling Inter-Chip Link -- 3D System Integration of a 90nm CMOS Processor and a 65nm CMOS SRAM --
Kiichi Niitsu (Keio Univ./JST), Yasuhisa Shimazaki (Keio Univ./Renesas Technology), Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga (Keio Univ.), Itaru Nonomura (Renesas Technology), Makoto Saen, Shigenobu Komatsu, Kenichi Osada, Naohiko Irie (Hitachi), Toshihiro Hattori, Atsushi Hasegawa (Renesas Technology), Tadahiro Kuroda (Keio Univ.) ICD2009-105
A 90nm CMOS processor is mounted face down on a package by C4 bump and a 65nm CMOS 1MB SRAM is glued on it face up. The ... [more] ICD2009-105
pp.163-168
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2009-12-03
15:20
Kochi Kochi City Culture-Plaza A Virus Scanning Engine Using a Parallel Sieve Method and the MPU
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.), Yoshifumi Kawamura (Renesas Technology Corp.) RECONF2009-45
In this paper, we show a new architecture for the virus scanning machine,
which is different from that of the intrusi... [more]
RECONF2009-45
pp.25-30
EMCJ 2009-11-20
14:20
Tokyo Aoyama Gakuin Univ. (Aoyama Campus) PDN Analysis of LSI Package in Short TAT using TMM and Approximated Equivalent Circuit
Masahiro Toyama, Yutaka Uematsu, Hideki Osaka (Hitachi,LTD.), Motoo Suwa, Atsushi Nakamura (Renesas Tech Corp.) EMCJ2009-84
For the efficient optimizing of LSI package PDN (Power Distribution Network) in early stage of the design, short TAT ana... [more] EMCJ2009-84
pp.31-36
ICD, ITE-IST 2009-10-02
13:55
Tokyo CIC Tokyo (Tamachi) [Invited Talk] Technical Trend of RF circuits
Satoshi Tanaka (Renesas Tech Corp.) ICD2009-54
This paper describes resent technology trend of mixed analog digital RF circuits. With progress of CMOS technology, larg... [more] ICD2009-54
pp.117-122
ICD, ITE-IST 2009-10-02
17:00
Tokyo CIC Tokyo (Tamachi) 100-1000 MHz Cutoff Frequency, 0-12 dB Boost Programmable Gm-C Filter with Digital Calibration for HDD Read Channel
Takahide Terada (Hitachi, Ltd.), Koji Nasu (Renesas Tech Corp.), Taizo Yamawaki, Masaru Kokubo (Hitachi, Ltd.) ICD2009-60
A programmable Gm-C filter with digital calibration for hard disk drive read channels was developed. The filter has gm a... [more] ICD2009-60
pp.153-157
LOIS, IE, ITE-ME, IEE-CMN 2009-09-24
13:30
Hiroshima Hiroshima Univ. Development of Range Finding System Using Monocular In-Vehicle Camera and LED
Shohei Watada, Ken-Ichiro Hayashi, Masashi Toda, Takeshi Nagasaki, Yuichi Mitsudo (Future Univ.-Hakodate), So Otsuka (Renesas Technology Corp.) LOIS2009-19 IE2009-60
Collisions often occur because the area behind a car is not clearly visible in the dark. In this paper, wepropose a syst... [more] LOIS2009-19 IE2009-60
pp.7-10
DC 2009-06-19
10:45
Tokyo Kikai-Shinko-Kaikan Bldg. Note on Yield and Area Trade-offs for MBIST in SoC
Masayuki Arai, Tatsuro Endo, Kazuhiko Iwasaki (Tokyo Metro. Univ.), Michinobu Nakao, Iwao Suzuki (Renesas Tech Corp.) DC2009-11
In this study we evaluate the effectiveness of hardware overhead reduction of memory BIST and spare assignment algorithm... [more] DC2009-11
pp.7-12
DC 2009-06-19
15:35
Tokyo Kikai-Shinko-Kaikan Bldg. Case study: Fault diagnosis for detecting systematic fault
Hiroshi Yamamoto, Hiroki Wada, Toru Ogushi, Michinobu Nakao (Renesas Tech. Corp.) DC2009-17
Fault diagnosis for products is important for yield learning of the deep sub-micron technology due to various failure mo... [more] DC2009-17
p.35
EMCJ 2009-06-05
14:50
Tokyo Tokyo Big Sight (Tokyo International Exihibition Center) Study for extracting the characteristics of LSI power supply at high frequency including the parasitic coupling between package and chip
Tomohiro Kita, Yuichi Mabuchi, Hiroshi Tanaka, Takashi Hisakado, Osami Wada (Kyoto Univ.), Atsushi Nakamura (Renesas Tech.) EMCJ2009-31
To establish more efficient EMC designing method of electronic apparatuses, constructing a precise EMC macromodel of IC/... [more] EMCJ2009-31
pp.51-56
ICD 2009-04-14
10:40
Miyagi Daikanso (Matsushima, Miyagi) A 0.56-V 128kb 10T SRAM Using Column Line Assist (CLA) Scheme
Shusuke Yoshimoto, Yusuke Iguchi, Shunsuke Okumura, Hidehiro Fujiwara, Hiroki Noguchi (Kobe Univ.), Koji Nii (Renesas Technology Corp.), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2009-6
We present a small-area 10T SRAM cell without half selection problem. As well, the proposed 10T cell achieves a faster a... [more] ICD2009-6
pp.27-32
VLD 2009-03-12
13:00
Okinawa   Emulation of Sequential Circuits by a Parallel Branching Program Machine
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.), Yoshifumi Kawamura (Renesas Technology Corp.) VLD2008-145
The parallel branching program machine~(PBM128) consists of 128 branching program machines~(BMs)
and a programmable in... [more]
VLD2008-145
pp.111-116
ICD, IPSJ-ARC, IPSJ-EMB 2009-01-14
16:30
Osaka Shoushin Kaikan A Low-Power Full-HD H.264 High-Profile Codec Based on a Heterogeneous Multiprocessor Architecture
Kenichi Iwata, Seiji Mochizuki, Motoki Kimura, Tetsuya Shibayama, Fumitaka Izuhara, Hiroshi Ueda (Renesas Tech Corp.), Koji Hosogi, Hiroaki Nakata, Masakazu Ehama (Hitachi Ltd.), Toru Kengaku, Takuichiro Nakazawa, Hiromi Watanabe (Renesas Tech Corp.) ICD2008-148
A video-size-scalable H.264 High-Profile codec including 19 application-specific CPUs for extensibility to multiple stan... [more] ICD2008-148
pp.111-116
AP, RCS
(Joint)
2008-11-19
13:25
Ishikawa Kanazawa Institute of Technology Adjacent channel rejection techniques for the IEEE802.11a/g OFDM system -- For multi-channel mesh network systems --
Minoru Kubo, Kazuyuki Takada, Takashi Okubo, Keisuke Furumi, Hiroshi Nogami, Hiroyasu Tominaga (Renesas Technology) RCS2008-131
IEEE802.11a/g wireless LAN system is greatly widespread. The number of allowed frequency channels are limited in each 2.... [more] RCS2008-131
pp.7-12
SDM [detail] 2008-11-14
13:50
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] [Invited]Robust Design of Embedded SRAM on Deep-submicron Technology
Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Hirofumi Shinohara (Renesas Technology Corp.) SDM2008-178
We develop high-density SRAM module in deep-submicron CMOS technology with the variation tolerant assist circuits agains... [more] SDM2008-178
pp.55-60
 Results 1 - 20 of 97  /  [Next]  
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