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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 8 of 8  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD 2017-04-21
10:25		 Tokyo   [Invited Lecture] A 6.05-Mb/mm2 16-nm FinFET Double Pumping 1W1R 2-port SRAM with 313ps Read Access Time
Yohei Sawada, Makoto Yabuuchi, Masao Morimoto (REL), Toshiaki Sano (RSD), Yuichiro Ishii, Shinji Tanaka (REL), Miki Tanaka (RSD), Koji Nii (REL) ICD2017-12		  [more] ICD2017-12
pp.63-65
DC 2017-02-21
12:00		 Tokyo Kikai-Shinko-Kaikan Bldg. An Approach to Performance Improvement of Machine Learning Based Fail Chip Discrimination
Daichi Yuruki, Satoshi Ohtake (Oita Univ), Yoshiyuki Nakamura (Renesas System Design) DC2016-77		 Today, advancements of semiconductor technology have progress to high integration of LSI circuits.
A technique which ke... [more]		 DC2016-77
pp.17-22
ICD, CPM, ED, EID, EMD, MRIS, OME, SCE, SDM, QIT
(Joint) [detail]		 2017-01-31
15:25		 Hiroshima Miyajima-Morino-Yado(Hiroshima) A 5.92-Mb/mm2 28-nm Pseudo 2-Read/Write Dual-Port SRAM Using Double Pumping Circuitry
Yuichiro Ishii, Makoto Yabuuchi, Yohei Sawada, Masao Morimoto, Yasumasa Tsukamoto (Renesas Electronics), Yuta Yoshida, Ken Shibata, Toshiaki Sano (Renesas System Design), Shinji Tanaka, Koji Nii (Renesas Electronics) EMD2016-86 MR2016-58 SCE2016-64 EID2016-65 ED2016-129 CPM2016-130 SDM2016-129 ICD2016-117 OME2016-98		 We propose pseudo dual-port (DP) SRAM by using 6T single-port (SP) SRAM bitcell with double pumping circuitry, which ena... [more] EMD2016-86 MR2016-58 SCE2016-64 EID2016-65 ED2016-129 CPM2016-130 SDM2016-129 ICD2016-117 OME2016-98
pp.87-92
ICD, SDM, ITE-IST [detail] 2016-08-03
13:20		 Osaka Central Electric Club [Invited Talk] A 16nm FinFET Heterogeneous Nona-Core SoC Supporting Functional Safety Standard ISO26262 ASIL B
Chikafumi Takahashi, Shinichi Shibahara, Kazuki Fukuoka, Jun Matsushima, Yuko Kitaji (Renesas System Design), Yasuhisa Shimazaki, Hirotaka Hara, Takahiro Irita (Renesas Electronics) SDM2016-64 ICD2016-32		 This paper presents an SoC for the next generation of car infotainment, achieving high performance powered by nine heter... [more] SDM2016-64 ICD2016-32
pp.105-110
ICD 2016-04-14
10:10		 Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Lecture] A Cost Effective Test Screening Method on 40-nm 4-Mb Embedded SRAM for Low-power MCU
Yuta Yoshida (RSD), Yoshisato Yokoyama, Yuichiro Ishii (Renesas Electronics), Toshihiro Inada, Koji Tanaka, Miki Tanaka, Yoshiki Tsujihashi (RSD), Koji Nii (Renesas Electronics) ICD2016-1		 An embedded single-port SRAM with cost effective test screening circuitry is demonstrated for low-power micr... [more] ICD2016-1
pp.1-6
SDM 2016-01-28
14:30		 Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] 2RW Dual-port SRAM Design Challenges in Advanced Technology Nodes
Koji Nii, Makoto Yabuuchi (Renesas), Yoshisato Yokoyama (Renesas System Design), Yuichiro Ishii, Takeshi Okagaki, Masao Morimoto, Yasumasa Tsukamoto (Renesas), Koji Tanaka, Miki Tanaka (Renesas System Design), Shinji Tanaka (Renesas) SDM2015-125		  [more] SDM2015-125
pp.21-25
SDM, ICD 2015-08-24
10:20		 Kumamoto Kumamoto City Development of a compacted doubly nesting array in Narrow Scribe Line aimed at detecting soft failures of interconnect via
Hiroki Shinkawata, Nobuo Tsuboi (REL), Atsushi Tsuda (RSD), Shingo Sato (Kansai), Yasuo Yamaguchi (REL) SDM2015-58 ICD2015-27		 We introduce a new addressable test structure array using for mass production stage which is compacted doubly nesting ar... [more] SDM2015-58 ICD2015-27
pp.7-10
ICD 2015-04-16
13:25		 Nagano   [Invited Lecture] A 512-kb 1-GHz 28-nm Partially Write Assisted Dual-Port SRAM with Self Adjustable Negative Bias Bitline
Shinji Tanaka (Renesas Electronics), Yuichiro Ishii, Makoto Yabuuchi (Renesas), Toshiaki Sano (Renesas System Design), Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Hirotoshi Sato (Renesas) ICD2015-2		  [more] ICD2015-2
pp.5-8
 Results 1 - 8 of 8  /   
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