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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2012-12-17 14:20 |
Tokyo | Tokyo Tech Front | A 250Msps, 0.5W eDRAM-based Search Engine applying full-route capacity dedicated FIB application Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto (Renesas), Koji Yamamoto (RDC), kazunari Inoue (Nara National College of Tech./Osaka Univ.)  ICD2012-91 |
[more] | ICD2012-91 pp.21-26 |
| NS, IN (Joint) |
2012-03-09 14:10 |
Miyazaki | Miyazaki Seagia | A Memory Controller with Guaranteed-Bandwidth Solution Hisashi Iwamoto, Yasuto Kuroda, Yuji Yano (Renesas), Koji Yamamoto (RDC), Shingo Ata (Osaka City Univ.), kazunari Inoue (Nara National College of Tec./Osaka Univ.) NS2011-258 |
Network traffic keeps increasing like as the demand of video streaming. Routers and switches in wire-line networks requi... [more] | NS2011-258 pp.445-450 |
| SDM, ICD | 2011-08-26 15:05 |
Toyama | Toyama kenminkaikan | A 28-nm dual-port SRAM macro with active bitline equalizing circuitry against write disturb issue Yuichiro Ishii, Hidehiro Fujiwara, Koji Nii (Renesas Electronics), Hideo Chigasaki, Osamu Kuromiya, Tsukasa Saiki (Renesas Design), Atsushi Miyanishi, Yuji Kihara (Renesas Electronics) SDM2011-92 ICD2011-60 |
We propose circuit techniques for an 8T dual-port (DP) SRAM to improve its minimum operating voltage (Vddmin). Active bi... [more] | SDM2011-92 ICD2011-60 pp.109-114 |
| NS, ICM, CQ (Joint) |
2010-11-19 13:20 |
Kyoto | Katsura Campus, Kyoto Univ. | Cost Evaluation and Parameter Optimization of the Fast Forwarding Engine using Standard Memory Kazuya Zaitsu (Osaka City Univ.), Koji Yamamoto (Renesas Design), Yasuto Kuroda, Kazunari Inoue (Renesas Electronics), Shingo Ata, Ikuo Oka (Osaka City Univ.) NS2010-101 |
Ternary content addressable memory (TCAM) is becoming very popular for designing high-throughput forwarding engines on ... [more] |
NS2010-101 pp.75-80 |
| ICD (Workshop) |
2010-08-16 - 2010-08-18 |
Overseas | Ho Chi Minh City University of Technology | A Multi-Color Space Conversion for Video Input Output Engine Hai Vu Nguyen, Thang Minh Le (RVC), Toyokazu Hori (REL) |
A Mutli-Color Space Conversion (CSC) in Video Input/ Output engine supports different conversion standards by only one l... [more] | |
| ICD (Workshop) |
2010-08-16 - 2010-08-18 |
Overseas | Ho Chi Minh City University of Technology | Designing an Interrupt Controller for a Multi-core System Liem Tan Pham, Huong Thien Hoang, Phong The Vo, Y Thien Vo (RVC), Masayuki Ito (REL) |
Enhancing design efficiency and overall system performance are important targets and design challenges for a multicore s... [more] | |
| ICD (Workshop) |
2010-08-16 - 2010-08-18 |
Overseas | Ho Chi Minh City University of Technology | Toward a High-Performance & Low-Power Application Processor for Portable Navigation Devices Khoa Dac Tran, Hoa Tan Lu, Cuong Phuc Phan, Quang Hai Phan (RVC), Hiroyuki Kudo, Seiichi Negishi, Mitsuyoshi Yamamoto, Yasushi Okamoto (REL) |
We have developed SH7723, an application processor for PND (portable navigation devices). SH7723 introduces a 720-MIPS S... [more] | |
| ICD (Workshop) |
2010-08-16 - 2010-08-18 |
Overseas | Ho Chi Minh City University of Technology | Three-speed-mode Infrared IP Supporting Single-frame and Multi-frame Operation Modes for Latest IrSimple Protocol Nam Hai Nguyen (RVC), Minoru Uemura, Kaoru Fukada, Yoshihiro Konno (REL) |
We have successfully developed an Infrared IP which integrates three speed modes: 1) Serial Infrared Rate (SIR) up to 11... [more] | |
| NS | 2010-05-21 10:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Hardware Implementation of Fast Forwarding Engine using Standard Memory and Dedicated Circuit Kazuya Zaitsu (Osaka City Univ.), Koji Yamamoto (Renesas Des.), Yasuto Kuroda, Kazunari Inoue (Renesas Ele.), Shingo Ata, Ikuo Oka (Osaka City Univ.) NS2010-26 |
Ternary content addressable memory (TCAM) is becoming very popular for designing high-throughput forwarding engines on r... [more] | NS2010-26 pp.59-64 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-04 14:05 |
Kochi | Kochi City Culture-Plaza | Logic stabilization way of open fault with unsuitable logic
-- Aim in simple diagnosis technology -- Masaru Sanada (Koch Univ. of Tech.), Keishi Hashida (Renesas Design), Taiki Yasutomi (Koch Univ. of Tech.) VLD2009-64 DC2009-51 |
An experiment for stabilization of output logic brought by floating gate fault with unsuitable electric value has been e... [more] | VLD2009-64 DC2009-51 pp.161-166 |
| ICD, SDM | 2009-07-16 11:25 |
Tokyo | Tokyo Institute of Technology | Low Energy Building Design in Packet Buffer Architecture with Deterministic Performance Guarantee Kazuya Zaitsu (Osaka City Univ.), Hisashi Iwamoto, Yasuto Kuroda, Yuji Yano (Renesas Technology), Koji Yamamoto (Renesas Design), Kazunari Inoue (Renesas Technology), Shingo Ata, Ikuo Oka (Osaka City Univ.) SDM2009-100 ICD2009-16 |
To design guaranteed high-performance router, it is problem that packet buffer is non-deterministic. We propose Head Buf... [more] | SDM2009-100 ICD2009-16 pp.17-22 |
| ICD | 2008-12-12 16:35 |
Tokyo | Tokyo Inst. Tech., Ohokayama Campus, Kokusa-Kouryu-Kaikan | Post-Silicon Programmed Body-Biasing Platform Suppressing Device Variability in 45 nm CMOS Technology Issei Kashima, Hiroaki Suzuki, Masanori Kurimoto (Renesas Technology Corp), Tadao Yamanaka (Renesas Design), Hidehiro Takata (Renesas Technology Corp), Hiroshi Makino (Osaka Institute of Tech), Hirofumi Shinohara (Renesas Technology Corp) ICD2008-128 |
The Post-Silicon Programmed Body-Biasing Platform is proposed to suppress device variability in the 45-nm CMOS technolog... [more] | ICD2008-128 pp.137-142 |
| VLD | 2008-09-29 13:30 |
Ishikawa | [Invited Talk]
Phase-Adjustable Error Detection Flip-Flops with 2-Stage Hold Driven Optimization and Slack Based Grouping Scheme for Dynamic Voltage Scaling Masanori Kurimoto, Hiroaki Suzuki (Renesas Technology), Rei Akiyama, Tadao Yamanaka, Haruyuki Okuma (Renesas Design), Hidehiro Takata, Hirofumi Shinohara (Renesas Technology) VLD2008-47 |
[more] | VLD2008-47 pp.1-6 |
|
| ICD, SDM | 2008-07-17 10:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A 45 nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka (Renesas Tech.), Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Katsuji Satomi, Hironori Akamatsu (Matsushita Elec.), Hirofumi Shinohara (Renesas Tech.) SDM2008-131 ICD2008-41 |
We develop 512 Kb SRAM module in 45 nm LSTP CMOS technology with the variation tolerant assist circuits against process ... [more] | SDM2008-131 ICD2008-41 pp.17-22 |
| ICD, SDM | 2007-08-24 08:55 |
Hokkaido | Kitami Institute of Technology | Fine-Grained In-Circuit Continuous-Time Probing Technique of Dynamic Supply Variation in SoCs Mitsuya Fukazawa, Tetsuro Matsuno, Toshifumi Uemura (Kobe Univ.), Rei Akiyama (Renesas Design), Tetsuya Kagemoto, Hiroshi Makino, Hidehiro Takata (Renesas Technology), Makoto Nagata (Kobe Univ.) SDM2007-156 ICD2007-84 |
Fine-grained built-in probing circuits are distributed at 120 locations on the SoC to allow continuous-time monitoring o... [more] | SDM2007-156 ICD2007-84 pp.85-90 |
| ICD, ITE-IST | 2007-07-27 11:10 |
Hyogo | A detachable high-speed wireless interface for LSI logic monitoring using pulse-based inductive-coupling technique Hiroki Ishikuro (Keio Univ.), Toshihiko Sugahara, Yoichi Takahata (Renesas Solutions Corp.), Shunichi Iwata (Renesas Technology Corp.), Yutaka Takikawa (Renesas Design Corp.), Tadahiro Kuroda (Keio Univ.) ICD2007-60 |
A detachable high-speed wireless interface was developed for monitoring of logic operation of a Si-chip through LSI pack... [more] | ICD2007-60 pp.135-140 |
|
| ICD | 2007-04-12 10:00 |
Oita | A high-density 1T-4MTJ MRAM with Self-Reference Sensing Scheme Yasumitsu Murai, Hiroaki Tanizaki (Renesas Design), Takaharu Tsuji, Jun Otani, Yuichiro Yamaguchi, Haruo Furuta, Shuichi Ueno, Tsukasa Oishi, Masanori Hayashikoshi, Hideto Hidaka (Renesas) ICD2007-3 |
A high-density memory cell named 1-Transistor 4-Magnetic Tunnel Junction (1T-4MTJ) has been proposed for Magnetic Random... [more] | ICD2007-3 pp.13-16 |
|
| ICD | 2007-04-13 09:40 |
Oita | [Invited Talk]
A 65 nm Embedded SRAM with Wafer Level Burn-In Mode, Leak-Bit Redundancy and E-trim Fuse for Known Good Die Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono (Renesas Technology), Yuji Oda (Shikino High-Tech), Susumu Imaoka (Renesas Design), Keiichi Usui (Daioh Electric), Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology) ICD2007-11 |
We propose a Wafer Level Burn-In (WLBI) mode, a leak-bit redundancy and a small, highly reliable Cu E-trim fuse repair s... [more] | ICD2007-11 pp.59-64 |
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| ICD, SDM | 2006-08-18 12:05 |
Hokkaido | Hokkaido University | A 65 nm Ultra-High-Density Dual-port SRAM with 0.71um2 8T-cell for SoC Susumu Imaoka (Renesas Design), Koji Nii (Renesas Technology), Yasuhiro Masuda (Renesas Design), Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Motoshige Igarashi, Kazuo Tomita, Nobuo Tsuboi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology) |
We propose a new access scheme of synchronous dual-port (DP) SRAM that minimizes area of 8T-DP-cell and keeps cell stabi... [more] | SDM2006-148 ICD2006-102 pp.133-136 |
| ICD, SDM | 2006-08-18 14:35 |
Hokkaido | Hokkaido University | A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits Makoto Yabuuchi, Shigeki Ohbayashi, Koji Nii, Yasumasa Tsukamoto (Renesas Technology), Susumu Imaoka (Renesas Design), Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Hiroshi Makino, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology) |
[more] | SDM2006-151 ICD2006-105 pp.149-153 |
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