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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 328  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM, ICD, ITE-IST [detail] 2021-08-18
13:00
Online Online [Invited Talk] A 12nm autonomous driving processor running 60.4 TOPS and 13.8 TOPS/W CNNs with task-separated ASIL D control
Katsushige Matsubara, Lieske Hanno (Renesas Electronics), Motoki Kimura (Renesas Electronics Europe), Atsushi Nakamura, Manabu Koike, Kazuaki Terashima, Shun Morikawa, Yoshihiko Hotta, Takahiro Irita, Seiji Mochizuki, Hiroyuki Hamasaki, Tatsuya Kamei (Renesas Electronics)
(To be available after the conference date) [more]
DC 2021-02-05
14:25
Online Online Fault Coverage Estimation Method in Multi-Cycle Testing
Norihiro Nakaoka, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima (Renesas Electronics Corp.) DC2020-75
 [more] DC2020-75
pp.36-41
SDM 2020-11-19
15:20
Online Online [Invited Talk] A technique for phase-detection auto focus under near-infrared-ray incidence in a back-side illuminated CMOS image sensor pixel
Tatsuya Kunikiyo, Hidenori Sato, Takeshi Kamino, Koji Iizuka, Ken'ichiro Sonoda, Tomohiro Yamashita (Renesas Electronics) SDM2020-26
A novel phase-detection auto focus (PDAF) technique for incident 850 nm plane wave is demonstrated using Ge-on-Si layer ... [more] SDM2020-26
pp.21-24
VLD, DC, RECONF, ICD, IPSJ-SLDM
(Joint) [detail]
2020-11-17
11:20
Online Online Control Point Selection Approach for Scan Pattern Reduction under Multi-cycle Test
Hikaru Tamaki, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima (Renesas) VLD2020-15 ICD2020-35 DC2020-35 RECONF2020-34
 [more] VLD2020-15 ICD2020-35 DC2020-35 RECONF2020-34
pp.24-29
DC 2020-02-26
10:25
Tokyo   Defective Chip Prediction Modeling Using Convolutional Neural Networks
Ryunosuke Oka, Satoshi Ohtake (Oita Univ.), Kouichi Kumaki (Renesas) DC2019-87
In recent years, the cost of LSI testing which guarantees reliability has relatively increased due to the development of... [more] DC2019-87
pp.7-12
DC 2020-02-26
11:35
Tokyo   Method for Inserting Fault-Detection-Strengthened Test Point under Multi-cycle Testing
Tomoki Aono, Norihiro Nakaoka, Shyu Saikou, Wang Senling, Higami Yoshinobu, Hiroshi Takahashi (Ehime Univ.), Hiroyuki Iwata, Youichi Maeda, Jun Matsushima (Renesas) DC2019-89
For guaranteeing the functional safety of an in-vehicle system, a power-on self-test (POST) is required to test the devi... [more] DC2019-89
pp.19-24
SDM 2020-02-07
09:35
Tokyo Tokyo University-Hongo [Invited Talk] Impact of Homogeneously Dispersed Al Nanoclusters by Si-monolayer Insertion into Hf0.5Zr0.5O2 Film on FeFET Memory Array with Tight Threshold Voltage Distribution
Tadashi Yamaguchi, Keiichi Maekawa, Takahiro Ohara, Atsushi Amo, Eiji Tsukuda, Kenichiro Sonoda, Hiroshi Yanagita, Masao Inoue, Masazumi Matsuura, Tomohiro Yamashita (Renesas) SDM2019-89
 [more] SDM2019-89
pp.5-8
SDM 2020-01-28
13:30
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Impact of Homogeneously Dispersed Al Nanoclusters by Si-monolayer Insertion into Hf0.5Zr0.5O2 Film on FeFET Memory Array with Tight Threshold Voltage Distribution
Keiichi Maekawa (renesas) SDM2019-83
 [more] SDM2019-83
pp.5-8
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2019-11-13
10:55
Ehime Ehime Prefecture Gender Equality Center VLD2019-31 DC2019-55 In testing of large scale integration (LSI) circuit, test escape detection using machine learning algorithms has been at... [more] VLD2019-31 DC2019-55
pp.13-18
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2019-11-14
16:10
Ehime Ehime Prefecture Gender Equality Center Analysis of Fault Detection Degradation Issue in Multi-cycle Test Scheme using Probabilistic Evaluation Method
Norihiro Nakaoka, Tomoki Aono, Sohshi Kudoh, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima (Renesas) VLD2019-45 DC2019-69
In order to ensure the functional safety of advanced autonomous driving systems, a power-on self-test
(POST) is require... [more]
VLD2019-45 DC2019-69
pp.145-150
SDM, ICD, ITE-IST [detail] 2019-08-07
16:30
Hokkaido Hokkaido Univ., Graduate School /Faculty of Information Science and [Invited Talk] High-temperature stable Physical Unclonable Functions with error-free readout scheme based on 28nm SGMONOS flash memory for security applications
Takahiro Shimoi, Tomoya Saito, Hirokazu Nagase, Masayuki Izuna, Akihiko Kanda, Takashi Ito, Takashi Kono (Renesas Electronics) SDM2019-39 ICD2019-4
Highly reliable Physical Unclonable Functions (PUF) based on 28nm Split-Gate MONOS (SG-MONOS) embedded flash memory is d... [more] SDM2019-39 ICD2019-4
pp.15-19
SDM, ICD, ITE-IST [detail] 2019-08-09
10:50
Hokkaido Hokkaido Univ., Graduate School /Faculty of Information Science and [Invited Talk] A 28nm 600MHz Automotive Flash Microcontroller with Virtualization-Assisted Processor for Next-Generation Automotive Architecture supporting ISO26262 ASIL-D
Naoto Okumura, Sugako Otani, Norimasa Otsuki, Yasufumi Suzuki, Shohei Maeda, Tomonori Yanagita, Takao Koike, Masao Ito, Minoru Uemura, Yasuhisa Shimazaki, Toshihiro Hattori, Noriaki Sakamoto, Hiroyuki Kondo (Renesas Electronics Corp.) SDM2019-47 ICD2019-12
Along with the rapid progress of automotive Electrical/Electronic(E/E) architecture, further integration of multiple ele... [more] SDM2019-47 ICD2019-12
pp.67-71
CAS, CS 2019-03-08
15:00
Kanagawa Shonan Institute of Technology [Special Invited Talk] The latest trends of Automotive Ethernet
Tomofumi Hokari, Nobukatsu Kitajima (Renesas) CAS2018-145 CS2018-113
To support Autonomous driving and Connected car applications, Automotive Ethernet has been adopted widely around the wor... [more] CAS2018-145 CS2018-113
p.39
DC 2019-02-27
09:25
Tokyo Kikai-Shinko-Kaikan Bldg. Variational Autoencoder-Based Efficient Test Escape Detection
Michihiro Shintani (NAIST), Kouichi Kumaki (Renesas Electronics Corporation), Michiko Inoue (NAIST) DC2018-72
 [more] DC2018-72
pp.7-12
DC 2019-02-27
14:05
Tokyo Kikai-Shinko-Kaikan Bldg. FF Toggle Control Point Selection Methods for Fault Detection Enhancement under Multi-cycle Testing
Tomoki Aono, Hanan T.Al-Awadhi, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima (Renesas) DC2018-79
Multi-cycle Test is a promising way to reduce the test volume of Logic-BIST (Logic Built-in Self-Test) based POST (Power... [more] DC2018-79
pp.49-54
SDM 2019-01-29
13:20
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Highly Reliable Ferroelectric Hf0.5Zr0.5O2 Film with Al Nanoclusters Embedded by Sub-Monolayer Doping Technique
Tadashi Yamaguchi, Tiantian Zhang, Kazuyuki Omori, Yasuhiro Shimada, Yorinobu Kunimune, Takashi Ide, Masao Inoue, Masazumi Matsuura (Renesas) SDM2018-86
Highly reliable ferroelectric (FE) Hf0.5Zr0.5O2 (HZO) film with Al nanoclusters embedded by sub-monolayer doping techniq... [more] SDM2018-86
pp.21-26
HWS
(2nd)
2018-12-13
15:05
Tokyo Tokyo Univ. Takeda Bldg. Takeda Hall Issues in industrial equipment installed in the factory and Renesas' initiatives
Tsukasa Yobo (Renesas Electronics)
(Advance abstract in Japanese is available) [more]
SDM 2018-11-08
09:20
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] SISPAD 2018 Review
Kenichiro Sonoda (Renesas Electronics) SDM2018-64
2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) was held on September 24-26,... [more] SDM2018-64
pp.1-6
SDM 2018-10-17
14:00
Miyagi Niche, Tohoku Univ. [Invited Talk] Fin-FET MONOS for Next Generation Automotive-MCU
Shibun Tsuda, Tomoya Saito, Hirokazu Nagase, Yoshiyuki Kawashima, Atsushi Yoshitomi, Shinobu Okanishi, Tomohiro Hayashi, Takuya Maruyama, Masao Inoue, Seiji Muranaka, Shigeki Kato, Takuya Hagiwara, Hirokazu Saito, Tadashi Yamaguchi, Masaru Kadoshima, Takahiro Maruyama, Tatsuyoshi Mihara, Hiroshi Yanagita, Kenichiro Sonoda, Yasuo Yamaguchi, Tomohiro Yamashita (Renesas) SDM2018-52
 [more] SDM2018-52
pp.1-5
SDM, ICD, ITE-IST [detail] 2018-08-08
13:15
Hokkaido Hokkaido Univ., Graduate School of IST M Bldg., M151 [Invited Lecture] A Highly Symmetrical 10T 2-Read/Write Dual-port SRAM Bitcell Design In 28nm High-k/Metal-gate Planar Bulk CMOS Technology
Yuichiro Ishii, Miki Tanaka, Makoto Yabuuchi, Yohei Sawada, Shinji Tanaka, Koji Nii (Renesas), Tien Yu Lu, Chun Hsien Huang, Shou Sian Chen, Yu Tse Kuo, Ching Cheng Lung, Osbert Cheng (UMC) SDM2018-40 ICD2018-27
We propose a highly symmetrical 10T 2-read/write (2RW) dual-port (DP) SRAM bitcell in 28-nm high-k/metal-gate planar bul... [more] SDM2018-40 ICD2018-27
pp.83-88
 Results 1 - 20 of 328  /  [Next]  
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