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Committee Date Time Place Paper Title / Authors Abstract Paper #
R 2007-09-14
11:20		 Kochi Kochi Univ. of Technology An idea of fault model by RC network, and the transistor level fault diagnosis trial.
Yutaka Yoshizawa (NEC Electoronics) R2007-31		 I introduce an idea of fault model by RC network. By using this model, not only short fault, resistive short/open fault ... [more] R2007-31
pp.11-16
ICD, CPM 2005-01-28
11:45		 Tokyo Kikai-Shinko-Kaikan Bldg. On Observability Quantification for Fault Diagnosis of VLSI Circuits
Naoya Toyota, Seiji Kajihara, Xiaoqing Wen (KIT), Masaru Sanada (NEC Electoronics) 		In most fault diagnosis, logic values can be observed at primary outputs and scan flip-flops as observation points. Howe... [more] CPM2004-167 ICD2004-212
pp.31-34
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