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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 4 of 4  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM 2008-06-10
10:55
Tokyo An401・402, Inst. Indus. Sci., The Univ. of Tokyo The role of the high-k/SiO2 interface in the control of the threshold voltage for high-k MOS devices
Kunihiko Iwamoto, Yuuichi Kamimuta (MIRAI-ASET), Yu Nunoshige (Shibaura Institute of Technology), Akito Hirano, Arito Ogawa, Yukimune Watanabe (MIRAI-ASET), Shinji Migita, Wataru Mizubayashi, Yukinori Morita (MIRAI-ASRC, AIST), Masashi Takahashi (MIRAI-ASET), Hiroyuki Ota (MIRAI-ASRC, AIST), Toshihide Nabatame (MIRAI-ASET), Akira Toriumi (The University of Tokyo) SDM2008-51
 [more] SDM2008-51
pp.53-58
SDM, VLD 2006-09-26
16:15
Tokyo Kikai-Shinko-Kaikan Bldg. To be announced
Masami Hane, Takeo Ikezawa, Michihito Kawada (NEC), Tatsuya Ezaki (Hiroshima Univ.), Toyoji Yamamoto (MIRAI-ASET)
Simulation analysis of channel-orientation effects on strained silicon MOSFETs based on a full-band Monte Carlo method c... [more] VLD2006-50 SDM2006-171
pp.65-69
SDM 2006-06-22
14:15
Hiroshima Faculty Club, Hiroshima Univ. unknown
Wataru Mizubayashi (MIRAI-ASRC, AIST), Arito Ogawa, Toshihide Nabatame, Hideki Satake (MIRAI-ASET), Akira Toriumi (MIRAI-ASRC, AIST, Univ. of Tokyo)
 [more] SDM2006-61
pp.107-111
ICD, SDM 2005-08-19
11:10
Hokkaido HAKODATE KOKUSAI HOTEL Improvement of threshold voltage asymmetry by Al compositional mudulation and partially silicided gate electrode for Hf-based high-k CMOSFETs
Masaru Kadoshima, Arito Ogawa, Masashi Takahashi (MIRAI-ASET), Hiroyuki Ota (MIRAI-ASRC, AIST), Nobuyuki Mise, Kunihiko Iwamoto (MIRAI-ASET), Shinji Migita (MIRAI-ASRC, AIST), Hideaki Fujiwara, Hideki Satake, Toshihide Nabatame (MIRAI-ASET), Akira Toriumi (MIRAI-ASRC, AIST, The Univ. of Tokyo)
Threshold voltage (Vth) tuning by engineering Fermi-level pinning (FLP) on HfAlOx(N) dielectrics is demonstrated for CMO... [more] SDM2005-148 ICD2005-87
pp.31-36
 Results 1 - 4 of 4  /   
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