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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 137  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
IA, SITE, IPSJ-IOT [detail] 2022-03-08
17:35
Kyoto Kyoto University, Yoshida Campus
(Primary: On-site, Secondary: Online)
Design and Implementation of User-Attracted Low-Latency MaaS Platform for Solving Social Issues
Hideto Yano, Tomoki Yoshihisa, Shinji Shimojo, Nao Takizaki, Yoshiyuki Kido (Osaka Univ.), Yukiko Kawai, Ryuta Yamaguchi (Kyoto Sangyo Univ.) SITE2021-67 IA2021-80
Mobility as a service (Maas), which has been attracting attention in recent years, can be utilized to solve social issue... [more] SITE2021-67 IA2021-80
pp.124-129
ICSS, IPSJ-SPT 2022-03-08
10:00
Online Online Input predictive attack by keyboard acoustic emanations using BERT and its countermeasures
Masahiro Iida (Teikyo Univ.), Mitsuaki Akiyama (NTT), Masaki Kamizono (DTCY), Takahiro Kasama (NICT), Yuichi Hattori (Secure Cycle Inc.), Hiroyuki Inoue (Kyoto Sangyo Univ.), Atsuo Inomata (Osaka Univ.) ICSS2021-67
The Keyboard Acoustic Emanations has been proposed to estimate the input key from keystroke sounds as a kind of side-cha... [more] ICSS2021-67
pp.49-54
MBE, NC
(Joint)
2022-03-04
14:20
Online Online Investigation of machine learning methods for emotion discrimination by using phase synchronization of electroencephalogram
Fumiya Hirooka, Jiro Okuda (Kyoto Sangyo Univ. Grad. Sch.) NC2021-74
This study investigated machine learning methods for emotion discrimination by using phase synchronization of electroenc... [more] NC2021-74
pp.143-148
DC 2022-03-01
13:45
Tokyo Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online)
A Logic Locking Method based on SFLL-hd at Register Transfer Level
Yohei Noguchi, Masayoshi Yoshimura (Kyoto Sangyo Univ.), Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.) DC2021-72
In recent years, with the increase of VLSI integration, LSI design companies utilize circuit design information, called ... [more] DC2021-72
pp.45-50
HCS 2022-01-28
15:20
Online Online Observation of verbal and non-verbal interactions related to Japanese food experience
Yasuyuki Sumi (Future Univ. Hakodate), Naomi Yamashita (NTT), Naoe Imura (Kyoto Sangyo Univ.), Akane Okuno (Future Univ. Hakodate) HCS2021-49
In order to deepen the understanding of verbal and nonverbal interactions related to the Japanese food experience, we ar... [more] HCS2021-49
pp.36-42
DC 2021-12-10
14:00
Kagawa
(Primary: On-site, Secondary: Online)
A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level
Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) DC2021-57
In recent years, to meet strict time-to-market constraints, it has become difficult for only one semiconductor design co... [more] DC2021-57
pp.13-18
IA 2021-09-08
14:25
Online Online Proposal of a Cloud Native IoT Architecture and its applications
Shinji Shimojo (Osaka Univ.), Ryuta Yamaguchi (Kyoto Sangyo Univ.), Nao Takizaki, Hideto Yano, Yoshiyuki Kido, Tomoki Yoshihisa (Osaka Univ.), Yukiko Kawai (Kyoto Sangyo Univ.), Yoshiyuki Masuda (Daikin), Matsuki Yamamoto (Osaka Univ.) IA2021-22
 [more] IA2021-22
pp.49-53
DE 2021-07-24
10:50
Kanagawa KAIT IT extension center (Hybrid)
(Primary: On-site, Secondary: Online)
DE2021-5 (To be available after the conference date) [more] DE2021-5
pp.22-27
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2021-03-26
12:00
Online Online A Logic Locking Method Based on Anti-SAT at Register Transfer Level
Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) CPSY2020-64 DC2020-94
In recent years, increasing circuit density, it has become difficult for only one semiconductor design company to design... [more] CPSY2020-64 DC2020-94
pp.85-90
DC 2021-02-05
15:30
Online Online A Don't Care Filling Method of Control Signals Based on Non-scan Field Testability at Register Transfer Level
Yuki Ikegaya, Yuta Ishiyama, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) DC2020-77
A field testing that monitors the values of circuit outputs and internal signal lines during function mode is used as on... [more] DC2020-77
pp.48-53
NC, NLP
(Joint)
2021-01-22
14:20
Online Online Contrast dependent spatial frequency tuning dynamics and its underlying neural mechanisms in the cat area 17
Kazuki Kohara, Seisiro Nitta, Hiroki Tanaka (Kyoto Sangyo Univ.) NC2020-40
In order to examine neural mechanisms to form spatial frequency (SF) tunings of area 17 neurons, we recorded extracellul... [more] NC2020-40
pp.45-48
IA 2020-10-01
15:35
Online Online [Poster Presentation] Research and development of Personal Data Store (PDS) with access control for advanced PLR of running data
Toyokazu Akiyama (Kyoto Sangyo Univ.), Yukiko Kawai (Kyoto Sangyo Univ./Osaka Univ.), Takumi Kiriu, Shinsuke, Nakajima (Kyoto Sangyo Univ.), Panote Siriaraya (Kyoto Institute of Tech.), Shinji Shimojo (Osaka Univ.) IA2020-9
 [more] IA2020-9
p.29
IA 2020-10-01
16:25
Online Online [Poster Presentation] Research and development of a safe bus driving support system considering passenger discomfort
Toyokazu Akiyama (Kyoto Sangyo Univ.), Ismail Arai (NAIST), Hiroshi Yamamoto (Ritsumeikan Univ.) IA2020-12
 [more] IA2020-12
p.32
CPSY, DC, IPSJ-ARC [detail] 2020-07-31
15:45
Online Online A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the number of Test Patterns
Ryuki Asami, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.) CPSY2020-12 DC2020-12
In recent years, as the high density and complexity of integrated circuits have increased, defects in cells have increas... [more] CPSY2020-12 DC2020-12
pp.75-80
CPSY, DC, IPSJ-ARC [detail] 2020-07-31
17:30
Online Online An Area Reduction Oriented Controller Augmentation Method Based on Functionally Equivalent Finite State Machine Generation
Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) CPSY2020-15 DC2020-15
In recent year, controller augmentation has been used for design-for-testability and design-for-security at register tra... [more] CPSY2020-15 DC2020-15
pp.93-98
DE 2020-06-27
11:00
Online Online DE2020-6  [more] DE2020-6
pp.31-34
DE 2020-06-27
11:15
Online Online DE2020-7  [more] DE2020-7
pp.35-40
DE 2020-06-27
11:35
Online Online DE2020-8  [more] DE2020-8
pp.41-46
HWS, VLD [detail] 2020-03-06
14:30
Okinawa Okinawa Ken Seinen Kaikan
(Cancelled but technical report was issued)
A Test Generation Method for Resistive Open Faults Using Partial MAX-SAT solver
Hiroshi Yamazaki, Yuta Ishiyama, Tatsuma Matsuta, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2019-131 HWS2019-104
In VLSI testing, stuck-at fault model and transition fault model have been widely used. However, with advance of semicon... [more] VLD2019-131 HWS2019-104
pp.215-220
NC, MBE
(Joint)
2020-03-05
10:45
Tokyo University of Electro Communications
(Cancelled but technical report was issued)
Effects of gaze queue in cognitive task on mirror neuron system
Taim Monobe, Hiroyuki Ito (Kyoto Sangyo Univ.) MBE2019-83
We report how the difference in visual information in a cognitive task influences the electroencephalogram (EEG) and the... [more] MBE2019-83
pp.11-16
 Results 1 - 20 of 137  /  [Next]  
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