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VLD 2014-03-05
15:45		 Okinawa Okinawa Seinen Kaikan A Case Study of Symbolic Model Checking for Verilog-HDL Hardware Design
Tomoyuki Yokogawa, Daichi Higashiyama (Okayama Pref. Univ.), Masafumi Kondo (Kawasaki Univ. of Medical Welfare), Yoichiro Sato, Kazutami Arimoto (Okayama Pref. Univ.) VLD2013-166		 In this paper, we show a case study where a design of 8bit microcomputer M8R, which is described by Verilog-HDL, is veri... [more] VLD2013-166
pp.177-182
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