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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, HWS [detail] 2022-03-07
09:35
Online Online Bottleneck Channel Routing to Reduce the Area of Analog VLSI
Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Yukichi Todoroki, Makoto Minami (Jedat)
Design automation that realizes analog integrated circuits to meet performance specifications in a small area is desired... [more] VLD2021-77 HWS2021-54
pp.7-12
SIP, CAS, VLD 2006-06-22
15:50
Hokkaido Kitami Institute of Technology Sequence-Pair Based Compaction under Equi-Length Constraint
Takehiko Matsuo (Univ. of Kitakyushu), Keiji Kida (Jedat), Tetsuya Tashiro, Shigetoshi Nakatake (Univ. of Kitakyushu)
Equi-length constraints are widely used for a sub-stitution for IR-drop or skew constrains. This paper provides a linear... [more] CAS2006-6 VLD2006-19 SIP2006-29
pp.29-34
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