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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 09:40 |
Oita | B-ConPlaza | Data Dependent Optimization using Suspicious Timing Error Prediction for Reconfigurable Approximation Circuits Kazushi Kawamura, Shin-ya Abe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)  VLD2014-80 DC2014-34 |
The propagation delay along each path inside an LSI widely varies depending on input data, and this property can be expl... [more] | VLD2014-80 DC2014-34 pp.51-56 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 10:05 |
Oita | B-ConPlaza | An Effective Robust Design Using Improved Checkpoint Insertion Algorithm for Suspicious Timing-Error Prediction Scheme and its Evaluations Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-81 DC2014-35 |
As process technologies advance, process and delay variation causes a complex timing design and in-situ timing error cor... [more] | VLD2014-81 DC2014-35 pp.57-62 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 14:45 |
Oita | B-ConPlaza | A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay Characteristics in FPGA Designs Koichi Fujiwara, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-85 DC2014-39 |
Recently, high-level synthesis (HLS) techniques for FPGA designs are required such as in image pro- cessing and computer... [more] | VLD2014-85 DC2014-39 pp.99-104 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 15:10 |
Oita | B-ConPlaza | A Process-Variation-Tolerant and Low-Latency Multi-Scenario High-level Synthesis Algorithm for HDR Architectures Koki Igawa, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-86 DC2014-40 |
In this paper, we propose a process-variation-tolerant and low-latency multi-scenario high-level synthesis algorithm for... [more] | VLD2014-86 DC2014-40 pp.105-110 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 16:15 |
Oita | B-ConPlaza | High speed design of sub-threshold circuit by using DTMOS Yuji Fukudome, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech), Masao Yanagisawa (Waseda Univ.) VLD2014-88 DC2014-42 |
Low power consumption is achieved by operating circuits in sub-threshold region. However, in sub-threshold region, the... [more] |
VLD2014-88 DC2014-42 pp.117-121 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 17:30 |
Oita | B-ConPlaza | A Hardware Trojans Detection Method focusing on Nets in Hardware Trojans in Gate-Level Netlists Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-91 DC2014-45 |
Recently, digital ICs are designed by outside vendors to reduce design costs in semiconductor industry. This circumstan... [more] |
VLD2014-91 DC2014-45 pp.135-140 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 15:10 |
Oita | B-ConPlaza | A Field Data Extractor Configuration Based on Multiplexer Tree Partitioning Koki Ito, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.), Yutaka Tamiya (Fujitsu Lab.) VLD2014-101 DC2014-55 |
As seen in packet analysis of TCP/IP offload engine and stream data processing of encoder/decoder for video data, it is ... [more] | VLD2014-101 DC2014-55 pp.197-202 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 15:35 |
Oita | B-ConPlaza | Energy-efficient High-level Synthesis Algorithm targeting HDR-mcv Architecture with Multiple Clock Domains and Multiple Supply Voltages Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Institute of Technology/Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-102 DC2014-56 |
An HDR-mcv architecture, which integrates multiple supply voltages and multiple clock domains into high-level synthesis ... [more] | VLD2014-102 DC2014-56 pp.203-208 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 16:00 |
Oita | B-ConPlaza | A High-level Synthesis Algorithm with Delay Variation Tolerance Optimization for RDR Architectures Yuta Hagio, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-103 DC2014-57 |
In this paper, we propose a high-level synthesis algorithm with delay variation tolerance optimization for RDR architect... [more] | VLD2014-103 DC2014-57 pp.209-214 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 09:15 |
Oita | B-ConPlaza | Energy evaluation of bit-write reduction method based on state encoding limiting maximum and minimum Hamming distances for non-volatile memories Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-105 DC2014-59 |
Data stored in non-volatile memories may be destructed due to crosstalk and radiation but we can restore their data by u... [more] | VLD2014-105 DC2014-59 pp.221-226 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 09:40 |
Oita | B-ConPlaza | Small-Sized Encoder/Decoder Circuit Design for Bit-Write Reduction Targeting Non-Volatile Memories Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-106 DC2014-60 |
Non-volatile memory has many advantages such as low leakage power and non-volatility. However, there are problems that ... [more] |
VLD2014-106 DC2014-60 pp.227-232 |
| IE, ICD, VLD, IPSJ-SLDM [detail] | 2014-10-02 13:25 |
Miyagi | Local pulse generation in variable stages pipeline designs for low energy consumption Takayuki Nii, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Univ.), Masao Yanagisawa (Waseda Univ.) VLD2014-61 ICD2014-54 IE2014-40 |
The increase of energy consumption due to improved performance has become a problem in the mobile terminal, and various ... [more] | VLD2014-61 ICD2014-54 IE2014-40 pp.7-12 |
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| CAS, SIP, MSS, VLD, SIS [detail] | 2014-07-11 14:00 |
Hokkaido | Hokkaido University | A floorplan-driven high-level synthesis algorithm for reducing multiplexer inputs targeting FPGAs Koichi Fujiwara, Shin-ya Abe, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) CAS2014-41 VLD2014-50 SIP2014-62 MSS2014-41 SIS2014-41 |
[more] | CAS2014-41 VLD2014-50 SIP2014-62 MSS2014-41 SIS2014-41 pp.219-224 |
| VLD | 2014-03-03 15:35 |
Okinawa | Okinawa Seinen Kaikan | Improved scan-based side-channel attack on the LED block cipher independent of scan structure Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-139 |
LED (Light Encryption Device) block cipher, one of lightweight block ciphers, is very compact in hardware. The conventio... [more] | VLD2013-139 pp.31-36 |
| VLD | 2014-03-03 16:00 |
Okinawa | Okinawa Seinen Kaikan | Latch-based AES Encryption Circuit Against Fault Analysis Youhua Shi, Hiroaki Taniguchi, Nozomu Togawa, Masao Yanagisawa (Waseda Univ.) VLD2013-140 |
In general, cryptography is considered to be secure because it is based on complicated mathematical theories. In recent ... [more] | VLD2013-140 pp.37-42 |
| VLD | 2014-03-03 16:25 |
Okinawa | Okinawa Seinen Kaikan | Secure scan design using improved random order scans and its evaluations Masaru Oya, Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-141 |
Scan test using scan chains is one of the most important DFT techniques. On the other hand, scan-based attacks are repo... [more] |
VLD2013-141 pp.43-48 |
| VLD | 2014-03-04 15:05 |
Okinawa | Okinawa Seinen Kaikan | Exposure source optimization by clustering for lithography Masashi Tawada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.), Takaki Hashimoto, Keishi Sakanushi, Shigeki Nojima, Toshiya Kotani (Toshiba) VLD2013-152 |
In lithography, we generate patterns on a wafer through a photomask, where patterns generated have to be close to ideal... [more] |
VLD2013-152 pp.105-110 |
| VLD | 2014-03-05 13:25 |
Okinawa | Okinawa Seinen Kaikan | Experiment and Analysis on Temperature Dependence of Delay and Energy for Subthreshold Circuits Hiroki Kushida, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech.), Masao Yanagisawa (Waseda Univ.) VLD2013-161 |
Low voltage design has been used in order to reduce the energy dissipation of mobile network equipment. However, as supp... [more] | VLD2013-161 pp.147-151 |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-29 13:20 |
Kanagawa | Hiyoshi Campus, Keio University | A Locality-Driven Task Mapping Algorithm for Multi-FPGA Systems Hiroki Katano, SeungJu Lee, Nozomu Togawa (Waseda Univ.), Takashi Aoki, Yusuke Sekihara, Mamoru Nakanishi (NTT) VLD2013-126 CPSY2013-97 RECONF2013-80 |
Recently, a scalable and reconfigurable multi-FPGA system has been proposed which consists of two or more boards, each ... [more] |
VLD2013-126 CPSY2013-97 RECONF2013-80 pp.143-148 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 14:55 |
Kagoshima | Suspicious timing error prediction using check points Hiroaki Igarashi, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-67 DC2013-33 |
Due to advance process technologies, timing design of LSIs has become more difficult and the importance of timing error ... [more] | VLD2013-67 DC2013-33 pp.39-44 |
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