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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 14:15 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | SAAV : Energy-efficient High-level Synthesis Algorithm targeting Adaptive Voltage Huddle-based Distributed Register Architecture with Dynamic Multiple Supply Voltages Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Institute of Technology Univ./Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)  VLD2012-82 DC2012-48 |
An adaptive voltage huddle-based distributed-register architecture (AVHDR architecture), which integrates dynamic multip... [more] | VLD2012-82 DC2012-48 pp.135-140 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 14:30 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | Energy Measurement and Analysis of ProcessingElement for Ultra Low Voltage Sachio Anzai, Masaru Kudo, Yuya Ota, Kazuki Ota, Kimiyoshi Usami (Sibaura Inst. Tech.) VLD2012-99 DC2012-65 |
The ALU of the ProcessingElement at 65nm process was operated by the ultra-low voltage, and delay time and survey of pow... [more] | VLD2012-99 DC2012-65 pp.231-236 |
| VLD | 2012-03-07 13:20 |
Oita | B-con Plaza | Power reduction of memory circuit and DVFS technique in Dynamic Reconfigurable Processor Yuki Hayakawa, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2011-138 |
This paper describes a DVFS technique to reduce energy dissipation of Dynamically Reconfigurable Processors(DRP). DRP’s ... [more] | VLD2011-138 pp.109-114 |
| VLD | 2012-03-07 15:15 |
Oita | B-con Plaza | Power-Switch Drive-circuit generation for Ground-Bounce reduction using the Genetic-Programming Makoto Miyauchi, Masaru Kudo, Yuya Ohta, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2011-142 |
Ground Bounce noise is a serious problem Power Gating technology. In this research, as compared with the Daisy Chain whi... [more] | VLD2011-142 pp.133-138 |
| VLD | 2012-03-07 16:05 |
Oita | B-con Plaza | Leakage Energy Reduction of Sub-Threshold Circuits by Body Bias Control for Power Switch Ryo Mitsuhashi, Masaru Kudo, Yuya Ohta, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2011-144 |
Power Gating (PG) is one of the technologies for reducing leakage energy. The effectiveness of leakage energy reduction ... [more] | VLD2011-144 pp.145-150 |
| VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2012-01-25 14:55 |
Kanagawa | Hiyoshi Campus, Keio University | Analysis of Power Domain Sizes on Multi-Vdd Variable-Pipeline Router Takeo Nakamura, Hiroki Matsutani (Keio Univ.), Mitihiro Koibuchi (NII), Kimiyoshi Usami (Shibaura Inst. of Tech.), Hideharu Amano (Keio Univ.) VLD2011-99 CPSY2011-62 RECONF2011-58 |
We have proposed a multi-voltage variable-pipeline router in order to reduce power consumption ofNetwork-on-Chip (NoC). ... [more] | VLD2011-99 CPSY2011-62 RECONF2011-58 pp.49-54 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 11:20 |
Miyazaki | NewWelCity Miyazaki | Power-Gating Circuit Scheme for Transient-Glitch Energy Reduction Yuya Ohta, Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2011-90 DC2011-66 |
In fine-grain power gating which performs cell-by-cell power gating (PG) , energy overhead consumed at sleep-in and slee... [more] | VLD2011-90 DC2011-66 pp.221-226 |
| RECONF | 2011-09-26 10:45 |
Aichi | Nagoya Univ. | Wavepipelining on A Ultra Low Power Reconfigurable Accelerator CMA-1. Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. of Tech.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (The Univ. of Electro-Communications) RECONF2011-22 |
CMA(Cool Mega-Array)-1 is a prototype media accelerator consisting of a large PE array which includes 24bit 8 × 8 PEs wi... [more] | RECONF2011-22 pp.1-6 |
| DC, CPSY (Joint) |
2011-07-29 09:00 |
Kagoshima | Reducing Leakage Power Consumption of Functional Units with Fine-grained Power Gating Weihan Wang (Keio Univ.), Yuya Ohta (Shibaura inst. of tech.), Lei Zhao (Keio Univ.), Yoshifumi Ishii (Keio univ.), Kimiyoshi Usami (Shibaura inst. of tech.), Hideharu Amano (Keio Univ.) CPSY2011-9 |
High speed power gating techniques are useful for reducing leakage power by functional units of CPU core. This paper pre... [more] | CPSY2011-9 pp.1-6 |
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| MSS, CAS, VLD, SIP | 2011-07-01 10:50 |
Okinawa | Okinawa-Ken-Seinen-Kaikan | [Panel Discussion]
Toward new developments of System and Signal Processing Subsociety Nagisa Ishiura (Kwansei Gakuin Univ.), Mitsunori Makino (Chuo Univ.), Kimiyoshi Usami (Shibaura Institute of Technology), Isao Yamada (Tokyo Institute of Technology), Kunihiko Hiraishi (JAIST), Shingo Yamaguchi (Yamaguchi Univ.), Masaki Nakamura (Toyama Pref. Univ.) CAS2011-22 VLD2011-29 SIP2011-51 MSS2011-22 |
[more] | CAS2011-22 VLD2011-29 SIP2011-51 MSS2011-22 p.127 |
| IPSJ-SLDM, VLD | 2011-05-18 15:45 |
Fukuoka | Kitakyushu International Conference Center | [Invited Talk]
Recent Gating-Techniques for Power Reduction Kimiyoshi Usami (Shibaura Inst. of Tech.) VLD2011-4 |
Key techniques to reduce power dissipation of LSIs are clock gating and power gating. In this talk, I will describe basi... [more] | VLD2011-4 pp.19-24 |
| RECONF | 2011-05-13 10:45 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | Optimization of Application Programs of SLD-1 : A Low Power Accelarator Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Tech. Univ.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Tokyo Univ. of Electro-Communication) RECONF2011-15 |
SLD(Silent Large Datapath)-1 is a prototype media accelerator consisting of a large PE array which includes 24bit 8 × 8 ... [more] | RECONF2011-15 pp.85-90 |
| VLD | 2011-03-02 15:30 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | Investigation and Evaluation of Sleep Signal Control based on a History Information for Fine-grain Power Gating Tetsuya Muto, Kimiyoshi Usami (Shibaura Inst. of Tech.) VLD2010-121 |
In Fine-grain Power Gating which reduces the leakage power by cutting Power Supply, Break Even Time(BET) which is the ti... [more] | VLD2010-121 pp.31-36 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-17 14:10 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Power reduction in Dynamically Reconfigurable Processor by Dynamically VDD Switching and a mapping technique to reduce energy overhead Tatsuya Yamamoto (Shibaura Institute), Kazuei Hironaka (Keio Univ.), Yuki Hayakawa (Shibaura Institute), Masayuki Kimura, Hideharu Amano (Keio Univ.), Kimiyoshi Usami (Shibaura Institute) VLD2010-92 CPSY2010-47 RECONF2010-61 |
This paper describes a dynamic VDD switching technique to reduce energy dissipation of Dynamically Reconfigurable Proces... [more] | VLD2010-92 CPSY2010-47 RECONF2010-61 pp.49-54 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 14:50 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Silent Large Datapath : A Ultra Low Power Accelarater Yoshihiro Yasuda, Nobuaki Ozaki, Masayuki Kimura, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. Tech.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Univ. of Electro-Communications) VLD2010-109 CPSY2010-64 RECONF2010-78 |
Silent Large Datapath (SLD) is a low power reconfigurable accelerator for high performance embedded systems. By using a... [more] |
VLD2010-109 CPSY2010-64 RECONF2010-78 pp.169-174 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 15:10 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Real Chip evaluation of Silent Large Datapath:A Ultra Low Power Accelarater Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. Tech.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Univ. of Electro-Communications) VLD2010-110 CPSY2010-65 RECONF2010-79 |
Battery driven multi-media applications require both high performance and energy efficiency. Recon-figurable... [more] | VLD2010-110 CPSY2010-65 RECONF2010-79 pp.175-180 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-11-30 14:15 |
Fukuoka | Kyushu University | Accurate Delay Analysis Method of Power-Gated Circuit Seidai Takeda, Kim Kyundong, Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. of Tech.) VLD2010-70 DC2010-37 |
We present a noble delay computation methodology for cluster-based power-gated circuit. Our scheme can compute circuit d... [more] | VLD2010-70 DC2010-37 pp.93-98 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-12-01 14:50 |
Fukuoka | Kyushu University | Optimal adder architecture in ultra low voltage domain Nao Konishi, Masaru Kudo, Kimiyoshi Usami (Shibaura Inst. Tech.) VLD2010-81 DC2010-48 |
Circuit performance is evaluated for several adder architectures with wiring capacitance extracted from layout at 65nm p... [more] | VLD2010-81 DC2010-48 pp.173-178 |
| VLD, IPSJ-SLDM | 2010-05-20 13:30 |
Fukuoka | Kitakyushu International Conference Center | Temperature-dependent model for break-even time in fine-grain power gating and adaptive control based on the temperature dependence Kimiyoshi Usami, Tatsunori Hashida (Shibaura Inst. Tech.) VLD2010-8 |
[more] | VLD2010-8 pp.73-78 |
| VLD | 2010-03-10 14:20 |
Okinawa | Circuit Structure of Level Shifter for Sub-threshold Operation Tomohiro Ishizaki, Satoshi Koyama, Kimiyoshi Usami (Shibaura Int. of Tech.) VLD2009-101 |
[more] | VLD2009-101 pp.13-18 |
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