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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 15:10 |
Oita | B-ConPlaza | A Process-Variation-Tolerant and Low-Latency Multi-Scenario High-level Synthesis Algorithm for HDR Architectures Koki Igawa, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)  VLD2014-86 DC2014-40 |
In this paper, we propose a process-variation-tolerant and low-latency multi-scenario high-level synthesis algorithm for... [more] | VLD2014-86 DC2014-40 pp.105-110 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 17:05 |
Oita | B-ConPlaza | Selection of Check Variables for Area-Efficient Soft-Error Tolerant Datapath Synthesis Junghoon Oh, Mineo Kaneko (JAIST) VLD2014-90 DC2014-44 |
As the device size decreases, the reliability degradation caused by soft-errors becomes one of the greatest issues in cu... [more] | VLD2014-90 DC2014-44 pp.129-134 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 15:35 |
Oita | B-ConPlaza | Energy-efficient High-level Synthesis Algorithm targeting HDR-mcv Architecture with Multiple Clock Domains and Multiple Supply Voltages Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Institute of Technology/Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-102 DC2014-56 |
An HDR-mcv architecture, which integrates multiple supply voltages and multiple clock domains into high-level synthesis ... [more] | VLD2014-102 DC2014-56 pp.203-208 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 16:00 |
Oita | B-ConPlaza | A High-level Synthesis Algorithm with Delay Variation Tolerance Optimization for RDR Architectures Yuta Hagio, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-103 DC2014-57 |
In this paper, we propose a high-level synthesis algorithm with delay variation tolerance optimization for RDR architect... [more] | VLD2014-103 DC2014-57 pp.209-214 |
| VLD, IPSJ-SLDM | 2014-05-29 11:05 |
Fukuoka | Kitakyushu International Conference Center | Proposal of a Synthesis Flow for Asynchronous Circuits with Bundled-Data Implementation from a SystemC Model Taichi Komine, Hiroshi Saito (Univ. of Aizu) VLD2014-5 |
This paper proposes a synthesis flow for asynchronous circuits with bundled-data implementation from a SystemC model to ... [more] | VLD2014-5 pp.21-26 |
| VLD | 2014-03-04 10:45 |
Okinawa | Okinawa Seinen Kaikan | An Approach of Rate-Distortion Optimized Quantization and its Evaluation Genki Moriguchi, Hajime Sawano, Takashi Kambe (Kinki Univ.), Gen Fujita (Osaka Electro-Comm. Univ.) VLD2013-145 |
Rate-distortion optimized quantization (RDOQ) is becoming a popular technology to improve its video coding performance. ... [more] |
VLD2013-145 pp.67-72 |
| VLD | 2014-03-05 10:00 |
Okinawa | Okinawa Seinen Kaikan | Area-Efficient Soft-Error Tolerant Datapath Design Based on Aggressive Resource Sharing Junghoon Oh, Mineo Kaneko (JAIST) VLD2013-156 |
As the device size decreases, the reliability problem caused by soft-errors becomes one of the big issues in current and... [more] | VLD2013-156 pp.119-124 |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-29 14:10 |
Kanagawa | Hiyoshi Campus, Keio University | Dynamic Operation Binding in Distributed Controller for Supporting Functional Units with Variable Latency Shinji Yamashita, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2013-128 CPSY2013-99 RECONF2013-82 |
This article presents a new distributed method for controlling circuits with variable latency units, which can dynamical... [more] | VLD2013-128 CPSY2013-99 RECONF2013-82 pp.155-160 |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-29 16:45 |
Kanagawa | Hiyoshi Campus, Keio University | Binary Synthesis of Hardware Accelerator Tightly Coupled with CPU Shimpei Tamura, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Kanbara (ASTEM), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2013-133 CPSY2013-104 RECONF2013-87 |
This article presents a method of synthesizing hardware that accelerates specified sections of binary programs. The acce... [more] | VLD2013-133 CPSY2013-104 RECONF2013-87 pp.185-190 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 15:20 |
Kagoshima | A controller design in high-level synthesis for multi-cycle transient fault tolerance Yutaro Ishimori, Tatsuya Nakaso, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2013-68 DC2013-34 |
This work discusses a design of the controller in a multi-cycle transient fault tolerant system. It focuses especially ... [more] |
VLD2013-68 DC2013-34 pp.45-50 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 09:45 |
Kagoshima | An Area Constraint-Based Fault-Secure HLS Algorithm for RDR Architectures Considering Trade-Off between Reliability and Time Overhead Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-79 DC2013-45 |
With process technology scaling, decreasing reliability caused by soft errors as well as increasing the average intercon... [more] | VLD2013-79 DC2013-45 pp.129-134 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-29 11:40 |
Kagoshima | Clock Energy-efficient High-level Synthesis and Experimental Evaluation for HDR-mcd Architecture Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech./Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-97 DC2013-63 |
In this paper, we propose a clock energy-efficient high-level synthesis algorithm for HDR-mcd architecture. In HDR-mcd,... [more] |
VLD2013-97 DC2013-63 pp.263-268 |
|
| IE, ICD, VLD, IPSJ-SLDM [detail] | 2013-10-08 09:00 |
Aomori | A High-Level Synthesis Algorithm with Post-Silicon Delay Tuning for RDR Architectures and its Experimental Evaluations Yuta Hagio, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-54 ICD2013-78 IE2013-54 |
As device feature size drops, interconnection delays often exceed gate delays. We have to incorporate interconnection ... [more] |
VLD2013-54 ICD2013-78 IE2013-54 pp.41-46 |
|
| RECONF | 2013-09-19 10:35 |
Ishikawa | Japan Advanced Institute of Science and Technology | Hardware Acceleration of Inverted Pendulum Control Processing by Using the High Level Synthesis Tool JavaRock Daichi Uetake, Takeshi Ohkawa (Utsunomiya Univ.), Takefumi Miyoshi (e-trees), Takashi Yokota, Kanemitsu Ootsu (Utsunomiya Univ.) RECONF2013-29 |
Microcontrollers are commonly used to develop robot control systems. However, microcontrollers do not meet recent requir... [more] | RECONF2013-29 pp.55-60 |
| VLD, IPSJ-SLDM | 2013-05-16 16:00 |
Fukuoka | Kitakyushu International Conference Center | A Zero Time and Area Overhead Fault-Secure High-Level Synthesis Algorithm for RDR Architectures Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-9 |
In this paper, we propose a zero time and area overhead fault-secure high-level synthesis algorithm for RDR architecture... [more] | VLD2013-9 pp.67-72 |
| VLD, IPSJ-SLDM | 2013-05-16 16:25 |
Fukuoka | Kitakyushu International Conference Center | SoC System Design Methodology with Fully-Coherent Cache Kodai Moritaka (NAIST), Hiroaki Yoshida, Mitsuru Tomono (FLA), Yasuhiko Nakashima (NAIST) VLD2013-10 |
As Chip Multi-Processors (CMPs) includes more processor cores in a single chip, the impact of its memory model on the en... [more] | VLD2013-10 pp.73-78 |
| VLD | 2013-03-05 16:25 |
Okinawa | Okinawa Seinen Kaikan | [Memorial Lecture]
Network Simplex Method Based Multiple Voltage Scheduling in Power-Efficient High-Level Synthesis Cong Hao, Song Chen, Takeshi Yoshimura (Waseda Univ.) VLD2012-153 |
In this work, we focus on the problem of latencyconstrained scheduling with consideration of multiple voltage technolo... [more] |
VLD2012-153 pp.93-98 |
| CPSY, VLD, RECONF, IPSJ-SLDM [detail] | 2013-01-16 16:25 |
Kanagawa | Speeding up multiple sections of binary code by hardware accelerator tightly coupled with cpu Shunsuke Satake (Kwansei Gakuin Univ), Nagisa Ishiura, Shimpei Tamura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ), Hiroyuki Kanbara (ASTEM) VLD2012-119 CPSY2012-68 RECONF2012-73 |
This article presents an improvement over the hardware accelerator tightly coupled with a CPU. While the previously pr... [more] |
VLD2012-119 CPSY2012-68 RECONF2012-73 pp.69-73 |
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| CPSY, VLD, RECONF, IPSJ-SLDM [detail] | 2013-01-17 14:25 |
Kanagawa | Implementation of a pupil detection method using an FPGA accelerator and a high-level synthesis tool Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) VLD2012-132 CPSY2012-81 RECONF2012-86 |
In this paper, we describe an implementation of a pupil detection using MaxCompiler which is a high-level synthesis fram... [more] | VLD2012-132 CPSY2012-81 RECONF2012-86 pp.147-152 |
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| CPSY, VLD, RECONF, IPSJ-SLDM [detail] | 2013-01-17 14:50 |
Kanagawa | Implementation of 3-D stencil computation with an FPGA accelerator and a high level synthesis tool Yoshihiro Nakamura, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) VLD2012-133 CPSY2012-82 RECONF2012-87 |
In this paper, we implemented a stencil computation kernel on an FPGA accelerator using MaxCompiler and MaxGenFD tools, ... [more] | VLD2012-133 CPSY2012-82 RECONF2012-87 pp.153-158 |
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