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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF | 2012-09-19 09:00 |
Shiga | Epock Ritsumei 21, Ritsumeikan Univ. | Effects of Power Saving by Dynamic Partial Reconfiguration in Video Shape Detection Processing Naoki Kawamoto, Kunihiro Ueda, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.)  RECONF2012-36 |
Some of recent FPGAs have the functionality of dynamic partial reconfiguration. By using this functionality, it is expec... [more] | RECONF2012-36 pp.73-78 |
| RECONF | 2012-09-19 15:05 |
Shiga | Epock Ritsumei 21, Ritsumeikan Univ. | Speedup of soft error tolerance evaluation with bootstrap method for FPGA systems Kohei Takano, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2012-45 |
SRAM-based field programmable gate arrays (FPGAs) are vulnerable to a single event upset (SEU). Although techniques for ... [more] | RECONF2012-45 pp.125-130 |
| DC, CPSY (Joint) |
2012-08-03 09:30 |
Tottori | Torigin Bunka Kaikan | A development scheduling simulater for reconfiguable system Takashige Uda, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) CPSY2012-19 |
Reconfigurable Computing Systems (RC Systems) are used to high-speed applications processing. We have investigating the ... [more] | CPSY2012-19 pp.61-66 |
| RECONF | 2012-05-29 15:10 |
Okinawa | Tiruru (Naha Okinawa, Japan) | Hard error avoidance for TMR module using dynamic relocation in an FPGA Hiroki Tanaka, Yoshihiro Ichinomiya, Sadaki Usagawa, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2012-11 |
FPGA can recover from hard-error by reconfiguring itself, avoiding the hard-error part.Especially, the fault recovery ca... [more] | RECONF2012-11 pp.61-66 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] | 2012-03-03 13:30 |
Miyagi | A Case Study of Supervisor Processor for Dependable System Makoto Fujino, Yoshihiro Ichinomiya, Hiroki Tanaka, Sayaka Yoshiura, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) CPSY2011-92 DC2011-96 |
Multicore processor is widely used in various systems. Although it will be used in harsh environment such as in-vehicle... [more] |
CPSY2011-92 DC2011-96 pp.199-204 |
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| VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2012-01-26 14:45 |
Kanagawa | Hiyoshi Campus, Keio University | Partial Reconfiguration and Its Application on a PC-FPGA Hybrid Cluster Ryo Ozaki, Akira Uejima, Masaki Kohata (Okayama Univ. of Sci.) VLD2011-116 CPSY2011-79 RECONF2011-75 |
Parallel processing by PC cluster and hardware acceleration by FPGA are useful technologies in a field of high performan... [more] | VLD2011-116 CPSY2011-79 RECONF2011-75 pp.147-152 |
| DC | 2011-12-16 15:40 |
Hyogo | Design of Flexible System Reconfiguration Using I<sup>2</sup>C Communication Yuta Takeda, Hiroshi Mochizuki (Nihon Univ.) DC2011-72 |
At present, a distributed control system that realizes more advanced work in real time is noted. And there are many res... [more] |
DC2011-72 pp.23-26 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-28 16:05 |
Miyazaki | NewWelCity Miyazaki | Fast soft-error recovery method for duplicated softcore processor system Yoshihiro Ichinomiya, Makoto Fujino, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2011-42 |
This paper presents a technique for ensuring the reliability of the softcore processor which implemented with SRAM-based... [more] | RECONF2011-42 pp.7-12 |
| ICD, IE, SIP, IPSJ-SLDM [detail] | 2011-10-24 14:45 |
Miyagi | Ｉｃｈｉｎｏｂｏ(Sendai) | Architecture of a Dynamically Reconfigurable VLSI Processor Based on Register-Transfer-Level Packet Transfer Yoshichika Fujioka (Hachinohe Inst. of Tech.), Sho Takizawa, Michitaka Kameyama (Tohoku Univ.) SIP2011-64 ICD2011-67 IE2011-63 |
Register-transfer-level packet routing scheme is proposed for intra-chip data transfer to make the size of configuration... [more] | SIP2011-64 ICD2011-67 IE2011-63 pp.13-18 |
| ICD, IE, SIP, IPSJ-SLDM [detail] | 2011-10-25 13:30 |
Miyagi | Ｉｃｈｉｎｏｂｏ(Sendai) | FPGA Platform for Heterogeneous Multicore Processors with MIMD-ALU-array-type Dynamically Reconfigurable Accelerators Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) SIP2011-73 ICD2011-76 IE2011-72 |
Heterogeneous multi-core architectures with CPUs and accelerators attract many attentions since they can achieve energy-... [more] | SIP2011-73 ICD2011-76 IE2011-72 pp.73-76 |
| ICD, IE, SIP, IPSJ-SLDM [detail] | 2011-10-25 13:55 |
Miyagi | Ｉｃｈｉｎｏｂｏ(Sendai) | Data-Transfer-Aware Memory Allocation for Dynamically Reconfigurable Accelerators in Heterogeneous Multicore Processors Yosuke Ohbayashi, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) SIP2011-74 ICD2011-77 IE2011-73 |
Accelerator cores in low-power heterogeneous multicore processors have multiple memory modules to increase the data acce... [more] | SIP2011-74 ICD2011-77 IE2011-73 pp.77-82 |
| OFT | 2011-10-20 15:45 |
Nagano | The development of optical signal monitor in GE-PON Kazuo Watanabe (SEOF), Hiroyuki Takahashi (NWX), Hiroyuki Takamori, Tomohiko Ueda (SEI) OFT2011-37 |
In recent years, numbers of cable networks reconfiguration is increasing with expansion of optical access network. We de... [more] | OFT2011-37 pp.31-34 |
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| RECONF | 2011-09-26 15:30 |
Aichi | Nagoya Univ. | Preemptive Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs - Hardware and Reconfiguration Layers Krzysztof Jozwik, Shinya Honda (Nagoya Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroaki Takada (Nagoya Univ.) RECONF2011-29 |
Preemption techniques for HW (hardware) tasks have been studied in order to improve their responsiveness and to allow ... [more] |
RECONF2011-29 pp.43-48 |
| RECONF | 2011-09-27 09:50 |
Aichi | Nagoya Univ. | A Basic Implementation of LUT-based Dynamic and Partial Reconfiguration from Remote Site Hiroyuki Kawai (Hamamatsu Photonics), Moritoshi Yasunaga (Tsukuba Univ.) RECONF2011-34 |
In this study we implement a mechanism that makes it possible to execute dynamic and partial reconfigurationfrom remote ... [more] | RECONF2011-34 pp.69-74 |
| PN, OCS, NS (Joint) |
2011-06-24 15:15 |
Wakayama | Wakayama University | Degraded Throughput Recovery Performance by ROADMs in Best-Effort CWDM Networks Shun Okimitsu, Shogo Kawai, Kazuto Nakai, Md. Nooruzzaman, Osanori Koyama, Yutaka Katsuyama (Osaka Prefecture Univ.) OCS2011-22 |
Congestion removing performance has been investigated in IP-over-CWDM networks with ROADMs under the best-effort transmi... [more] | OCS2011-22 pp.59-64 |
| RECONF | 2011-05-12 13:30 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | Context Synchronization Method for Reliable Softcore Processor System Makoto Fujino, Noritaka Kai, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2011-5 |
SRAM-based FPGAs are vulnerable to a SEU, which is induced by radiation effect. The SEU's effects on configuration mem... [more] |
RECONF2011-5 pp.25-30 |
| RECONF | 2011-05-12 15:00 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | Design and Implementation of a Portable Framework for PCI Express Interface Shoichi Igarashi, Ryuhei Morita, Yuichi Okuyama (Univ. of Aizu), Tsuyoshi Hamada (Nagasaki Univ.), Junji Kitamichi, Kenichi Kuroda (Univ. of Aizu) RECONF2011-8 |
In this paper, we propose a portable framework for PCI Express interface. The proposed framework provides DMA transfer a... [more] | RECONF2011-8 pp.43-48 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 10:20 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Evaluation of switchable AES S-box circuit using dynamic and partial reconfiguration Naoko Yamada (Keio Univ.), Keisuke Iwai, Takakazu Kurokawa (NDA), Hideharu Amano (Keio Univ.) VLD2010-102 CPSY2010-57 RECONF2010-71 |
Recently, the threat of side channel attack to the hardware encryption circuits is increasing. In order to cope with it... [more] |
VLD2010-102 CPSY2010-57 RECONF2010-71 pp.127-132 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 14:30 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Implementation of Dynamic Reconfigurable Processor with Multi-Accelerator Shuhei Igari, Junji Kitamichi, Yuichi Okuyama, Kenichi Kuroda (Aizu Univ.) VLD2010-108 CPSY2010-63 RECONF2010-77 |
Recently, System on a Chip (SoC) has problems increasing of the scale of circuit and design cost, because SoC contains m... [more] | VLD2010-108 CPSY2010-63 RECONF2010-77 pp.163-168 |
| DC | 2010-12-10 15:40 |
Tottori | International Family Plaza (Yonago) | Design and Implementation of a Distributed Control System for Flexible System Reconfiguration Yuta Takeda, Hiroshi Mochizuki, Hideo Nakamura (Nihon Univ.) DC2010-55 |
At present, a distributed control system that realizes more advanced work in real time is noted. And there are many rese... [more] | DC2010-55 pp.21-24 |
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