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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| MW | 2009-11-20 09:00 |
Kagoshima | Tanegashima | Generation of Wideband Signal using Coherent Multi-Carrier Modulation Hidehisa Shiomi, Ryo Tachibana, Yasuyuki Okamura (Osaka Univ.)  MW2009-135 |
Recently, the demand for a broadband arbitrary signal generation technique over Gbps has grown as the broadband communic... [more] | MW2009-135 pp.43-46 |
| OPE, LQE, OCS | 2009-10-23 14:20 |
Fukuoka | Phase Chain of Phase-Locked Multi-carriers Synchronizing to Optical Frequency Comb Reference spaced at 25GHz Takuzi Sudaki, Akira Mizutori, Masafumi Koga (Oita Univ.) OCS2009-74 OPE2009-140 LQE2009-99 |
This paper proposed an optical phase chain technique for multiple phase-locked multi-carriers that synchronized to optic... [more] | OCS2009-74 OPE2009-140 LQE2009-99 pp.167-170 |
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| MW | 2009-09-25 13:50 |
Tokyo | Univ. of Electro-Communications | A Low-Power, Small Area Quadrature LC-VCO using miniature 3D Solenoid shaped Inductor Akira Tanabe, Ken'ichiro Hijioka, Hirokazu Nagase, Yoshihiro Hayashi (NEC Electronics Corp.) MW2009-83 |
An extra small area, low-power 5GHz Quadrature LC-VCO and PLL have been fabricated using 3 dimensional (3D) solenoid sha... [more] | MW2009-83 pp.55-60 |
| MW | 2009-09-25 17:40 |
Tokyo | Univ. of Electro-Communications | [Special Talk]
Frequency and Phase Difference Control Using Fractional-N PLL Synthesizers by Composition of Control Data Kenichi Tajima, Ryoji Hayashi (Mitsubishi Electric Corp.) MW2009-91 |
A novel phase control technique of LO signals using a Fractional-N PLL(F-PLL) synthesizer is described. In multiple, pa... [more] | MW2009-91 pp.99-104 |
| CAS, NLP | 2009-09-25 13:25 |
Hiroshima | Hiroshima Univ. Higashi Senda Campus | An experimental study of the CMOS PLL as an FM demodulator for Gaussian noise genaration Akio Takada (Hakodate Nat. Col. of Tech.), Tetsuro Endo (Meiji Univ.) CAS2009-43 NLP2009-79 |
There have been reports on the numerical and experimental results concerning white noise generation from chaotic PLLs. ... [more] | CAS2009-43 NLP2009-79 pp.109-114 |
| NLP | 2009-03-11 16:20 |
Kyoto | Experimental Study of White Noise Generation Using a CMOS PLL Akio Takada (Hakodate Nat.Col. of Tech.), Tetsuro Endo (Meiji Univ.) NLP2008-170 |
White noise can be characterized as a random signal that has uniform power spectral density at every frequency in the ra... [more] | NLP2008-170 pp.111-116 |
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| SIP, RCS | 2009-01-22 14:30 |
Kumamoto | Kumamoto University | Timing jitter dependency on PLL bandwidth Isamu Wakabayashi, Kazuhiro Miyauchi (Tokyo Univ. of Science) SIP2008-137 RCS2008-185 |
Timing jitter of digital transmission systems has three components SS, SN and NN typically. The authors reported in a pr... [more] | SIP2008-137 RCS2008-185 pp.77-82 |
| US | 2008-12-19 13:30 |
Kanagawa | Practical configuration and design of liquid level meter using the flexural vibrations in a rod Kentaro Nakamura, Daisuke Koyama, Sadayuki Ueha (Tokyo Tec), Kazumitsu Nukui (JAF), Kenzo Ikeda (Taiyo Nissan) US2008-67 |
Resonance frequency of a flexural vibrating rod is lowered by immersing the rod into fluid because of the mass effect of... [more] | US2008-67 pp.1-6 |
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| ICD, ITE-IST | 2008-10-24 12:30 |
Hokkaido | Hokkaido University | All digital PLL with independent loop characteristic by using fine clock-period comparator Yukinobu Makihara, Masayuki Ikebe, Junichi Motohisa, Eiichi Sano (Hokkaido Univ.) ICD2008-87 |
We proposed new architecture of phase-locked loop (PLL) by using clock-period comparison. For a digitally controlled PLL... [more] | ICD2008-87 pp.165-170 |
| VLD, ICD | 2008-03-06 10:30 |
Okinawa | TiRuRu | Design and Evaluation of the component circuits for the PLL Yuko Kitaji, Masayoshi Tachibana (Kochi Univ. of Tech.) VLD2007-147 ICD2007-170 |
The PLL circuit consists of the phase detector, the loop filter, the voltage-controlled oscillator, and the divider. In ... [more] | VLD2007-147 ICD2007-170 pp.19-24 |
| NLP | 2008-01-31 16:40 |
Hokkaido | Frequency spectra of chaotic oscillations in the PLL circuit driven with a non-sinusoidal signal Akio Takada, Kazuya Unjo (Hakodate Nat.Col. of Tech.) NLP2007-137 |
It has been reported that the white noise can be generated from the chaotic PLL circuit of which the dynamics is compati... [more] | NLP2007-137 pp.45-50 |
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| ICD, ITE-CE | 2007-12-13 15:45 |
Kochi | Low-jitter and Large-EMI-reduction Spread-spectrum Clock Generator with Auto-calibration for Serial-ATA Application Takashi Kawamoto (Hitachi), Takayuki Noto, Hiromitsu Inada, Tomoaki Takahashi (Renesas) ICD2007-125 |
An low jitter voltage-controlled oscillator (VCO) with high-frequency-limiter and an auto-calibration technique suitable... [more] | ICD2007-125 pp.31-36 |
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| ICD, SDM | 2007-08-23 11:10 |
Hokkaido | Kitami Institute of Technology | Multiphase-Output Level Shift System used in Multiphase PLL for Low Power Application Akinori Matsumoto, Shiro Sakiyama, Yusuke Tokunaga, Takashi Morie, Shiro Dosho (Matsushita) SDM2007-146 ICD2007-74 |
Low power design is essential for mobile application. For a PLL with multiphase outputs, level shifter (LS), which conve... [more] | SDM2007-146 ICD2007-74 pp.29-34 |
| SANE | 2007-07-27 15:40 |
Tokyo | Electric Navigation Research Institute | PLL simulation for GPS signal in the presence of Ionospheric Scintillation Shunichiro Kondo, Takuji Ebinuma, Nobuaki Kubo, Akio Yasuda (Tokyo Marine Univ) SANE2007-56 |
Ionospheric scintillation is one of the serious issues in GPS positioning. It induces a rapid change in the amplitude an... [more] | SANE2007-56 pp.25-30 |
| ICD, ITE-IST | 2007-07-27 09:45 |
Hyogo | A PVT Tolerant PLL with On-Chip Loop-Transfer-Function Calibration Circuit M.Kondou (Fujitsu Laboratoried Ltd), T.Mori (Fujitsu Limited) ICD2007-57 |
A PVT tolerant PLL architecture which uses two on-chip digital calibration circuits to maintain loop transfer function i... [more] | ICD2007-57 pp.117-121 |
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| SR | 2007-07-27 16:55 |
Kanagawa | Studies on the Phase Noise and Spurious Level Behavior of an All Digital Phase Locked Loop Michael Zamrowski (Johannes Gutenberg Univ.), Tsuyoshi Terao, Kiyomichi Araki (Tokyo Inst. of Tech.) SR2007-45 |
An All Digital Phase Locked Loop (ADPLL) was proposed being suitable for a CMOS processed system on one chip digital RF ... [more] | SR2007-45 pp.157-162 |
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| EE | 2007-07-19 16:40 |
Yamaguchi | A Novel Real-Time Detection Method of Active and Reactive Current for Single-Phase Active Power Filters Yasushi Omura (Niihama National Coll. Tech.), Toshihiko Tanaka (Ymaguchi Univ.), Eiji Hiraki, Norio Ishikura (Yamaguchi Univ.), Masayoshi Yamamoto (Shimane Univ.) EE2007-14 |
This paper proposes the simplest real-time detection method of the fundamental active and reactive currents in single-ph... [more] | EE2007-14 pp.39-44 |
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| RCS, IN (Joint) |
2007-05-17 15:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Timing jitter in PAM, ASK and QAM schemes, No.2. In case of cosine roll-off transmission Isamu Wakabayashi, Kazuhiro Miyauchi (TUS) RCS2007-1 |
Timing jitter in MPAM, MASK and M^{2}QAM with AWGN is calculated for a cosine roll-off bandlimiting scheme. Jitter varia... [more] | RCS2007-1 pp.1-6 |
| MW, SCE | 2007-04-27 09:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Phase Noise and Spurious Level Characteristics in All-Digital PLL Tsuyoshi Terao, Kiyomichi Araki (Tokyo Inst. of Tech.) SCE2007-1 MW2007-1 |
All-Digital PLL(ADPLL) has been proposed for local oscillators of digital RF transceivers, which are suitable for CMOS s... [more] | SCE2007-1 MW2007-1 pp.1-6 |
| NLP | 2006-12-13 16:55 |
Hokkaido | Energy-based analysis of frequency entrainment described by van der Pol and PLL equations Yoshihiko Susuki, Yuuichi Yokoi, Takashi Hikihara (Kyoto Univ.) |
This paper is devoted to an analysis of frequency entrainment described by van der Pol and PLL equations. The frequency... [more] | NLP2006-100 pp.57-62 |
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