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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| COMP | 2009-03-02 10:35 |
Tokyo | Tokyo Institute of Technology | Efficient Enumeration of All Ladder Lotteries Katsuhisa Yamanaka (Univ. of Electro-Comm.), Shin-ichi Nakano (Gunma Univ.), Yasuko Matsui (Tokai Univ.), Ryuhei Uehara (JAIST), Kento Nakada (Kyoto Univ.)  COMP2008-56 |
A ladder lottery, known as the "Amidakuji" in Japan, is a common way to choose a random permutation. Given a permutation... [more] | COMP2008-56 pp.17-23 |
| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-30 09:40 |
Kanagawa | Foreknown Regularity Arithmetic Processing Unit Jin Sato, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.) VLD2008-111 CPSY2008-73 RECONF2008-75 |
The paper proposes a method of designing an arithmetic unit based on the regularity of the output depending on input pat... [more] | VLD2008-111 CPSY2008-73 RECONF2008-75 pp.117-122 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 10:55 |
Fukuoka | Kitakyushu Science and Research Park | Evaluation of Hardware Algorithms on a Circuit Model Considering Wire Delay Tetsuya Nagase, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ.) VLD2008-77 DC2008-45 |
In the design of integrated circuits, it is important to design or choose algorithms according to the requirements such ... [more] | VLD2008-77 DC2008-45 pp.103-108 |
| MW | 2008-06-27 13:40 |
Aichi | Toyohashi Univ. of Tech. | Phase Frequency Characteristics formulation and Active Q-Factor for Ladder Phase Shift Circuits Yoshitada Iyama (Kumamoto National College of Tech.) MW2008-41 |
Phase frequency characteristics formulation for ladder phase shift circuits is presented. The results indicate that a de... [more] | MW2008-41 pp.53-57 |
| DC | 2008-06-20 14:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg | Test generation for multi-operand adders consisting of full adders Nobutaka Kito, Naofumi Takagi (Nagoya Univ.) DC2008-14 |
Level-testability of multi-operand adders consisting of carry save adders is shown by showing test design for it. Carry ... [more] | DC2008-14 pp.19-22 |
| VLD, ICD | 2008-03-06 12:00 |
Okinawa | TiRuRu | Area/Delay/Power Consumption Tradeoff for Multiplier with Tree-structured Partial-product Adders Masayoshi Tachibana (kochi University of Technology) VLD2007-150 ICD2007-173 |
In this paper we address the area, delay and power consumption tradeoff for multiplier with tree-structured partial prod... [more] | VLD2007-150 ICD2007-173 pp.37-42 |
| CAS | 2008-02-01 09:50 |
Okinawa | A High Fidelity Estimation Method for Interconnect Delays with a Ramp Input Daisuke Orui, Shuji Tsukiyama (Chuo Univ.) CAS2007-96 |
With the progress of micro-technologies, the importance of interconnect design has been increasing. Since delays must b... [more] | CAS2007-96 pp.13-18 |
|
| SCE | 2008-01-25 15:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Design and implementation of the SFQ half-precision floating point adder Heejoung Park, Yuki Yamanashi, Kazuhiro Taketomi, Nobuyuki Yoshikawa (Yokohama National Univ.), Masamitsu Tanaka, Koji Obata, Yuki Itou, Akira Fujimaki, Naofumi Takagi, Kazuyoshi Takagi (Nagoya Univ.) |
A new project was started to develop a large-scale reconfigurable data-path (LSRDP) based on the single-flux-quantum (SF... [more] | SCE2007-31 pp.35-40 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-22 13:50 |
Fukuoka | Kitakyushu International Conference Center | Parallel prefix adder synthesis based on Ling’s carry computation Taeko Matsunaga, Shinji Kimura (Waseda Univ.), Yusuke Matsunaga (Kyushu Univ.) |
Ling adders calculate carry propagation based on adjacent bit pairs, and can be formulated as parallel prefix adders. I... [more] |
VLD2007-97 DC2007-52 pp.49-54 |
| CAS, SIP, VLD | 2007-06-22 13:20 |
Hokkaido | Hokkaido Tokai Univ. （Sapporo) | Arithmetic Module Generation Using Optimized Parallel Prefix Adders Yuki Watanabe, Naofumi Homma, Takafumi Aoki (Tohoku Univ.), Tatsuo Higuchi (Totech) CAS2007-27 VLD2007-43 SIP2007-57 |
This paper presents an arithmetic module generator using parallel prefix adders. In the proposed system, parallel prefix... [more] | CAS2007-27 VLD2007-43 SIP2007-57 pp.49-54 |
| MW | 2007-05-21 13:55 |
Hyogo | University of Hyogo | A Design Method of Lumped-Element Wilkinson Power Dividers Using LC-Ladder Circuits Tadashi Kawai, Yasuaki Nakashima, Yoshihiro Kokubo, Isao Ohta (Univ. of Hyogo) MW2007-13 |
This paper treats a novel lumped-element Wilkinson power divider using LC-ladder circuis. The proposed circuit consists ... [more] | MW2007-13 pp.7-10 |
| VLD, IPSJ-SLDM | 2007-05-11 11:45 |
Kyoto | Kyodai Kaikan | On power-conscious approach for prefix graph synthesis Taeko Matsunaga (Waseda Univ), Yusuke Matsunaga (Kyushu Univ.) |
A prefix graph visualizes a global structure of a parallel prefix adder at technology independent level. Several approa... [more] |
VLD2007-12 pp.31-36 |
| ICD, VLD | 2007-03-09 08:40 |
Okinawa | Mielparque Okinawa | Easily Testable Multiplier with 4-2 Adder Tree Nobutaka Kito, Kensuke Hanai, Naofumi Takagi (Nagoya Univ.) |
The growth of the scale of VLSI designs makes test cost of VLSI chips expensive. Techniques of test cost reduction are r... [more] | VLD2006-140 ICD2006-231 pp.1-6 |
| NLP | 2007-03-06 10:15 |
Miyagi | Resistive ladder D/A converters for floating-point representation Hiroyuki Tomura, Toshimichi Saito (Hosei Univ.) |
This paper presents a circuit model of a floating-point resistive ladder D/A converter. In the circuit, the mantissa i... [more] |
NLP2006-157 pp.17-20 |
|
| SCE | 2007-01-26 10:55 |
Tokyo | SRL | Design and Implementation of Bit-Slice Adder Heejoung Park, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama National Univ.), Masamitsu Tanaka, Akira Fujimaki (Nagoya Univ.), Hirotaka Terai (NICT), Shinichi Yorozu (NEC) |
Recently, a lot of researches on designing digital circuits by using SFQ logic circuits have been carried out extensivel... [more] | SCE2006-32 pp.13-18 |
| MBE | 2007-01-26 17:40 |
Kagoshima | Kagoshima-Shichoson-Jichi-Kaikan Bldg. | Closed bellows pressure sensor telemeter transmitter for unconstrained continuous monitoring of intracorporeal pressure Koya Nakazono (Kagoshima Univ.), Seiji Matsumoto, Hirotsugu Uemura (Kinki Univ.), Yasuhito Takeuchi (Kagoshima Univ.) |
Abstract: Noninvasive, non-disturbing urodynamics study still has many unsolved burdens since urinal accumulation and vo... [more] | MBE2006-117 pp.85-88 |
| ICD, SIP, IE, IPSJ-SLDM | 2006-10-27 09:20 |
Miyagi | On synthesis algorithm for parallel prefix adders using dynamic programming Taeko Matsunaga (FLEETS), Yusuke Matsunaga (Kyushu Univ.) |
This paper addresses parallel prefix adder synthesis which targets area minimization under given timing constraints. Th... [more] | SIP2006-102 ICD2006-128 IE2006-80 pp.7-12 |
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| NLP, CAS | 2006-10-05 11:40 |
Osaka | Sorter-based Sigma-Delta Domain Multi-level Operators - Part I Hisato Fujisaka, Takeshi Kamio, Kazuhisa Haeiwa (Hiroshima City Univ.) |
This paper presents a multi-level adder as a fundamental circuit module for sigma-delta domain signal processing.Binary ... [more] | CAS2006-40 NLP2006-63 pp.35-40 |
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| WBS, IT, ISEC | 2006-03-17 15:00 |
Aichi | Nagoya Univ. | A Recursive Construction of Error-Correcting Signature Code for Multiple-Access Adder Channel Daisaku Toda, Jun Cheng, Yoichiro Watanabe (Doshisha Univ.) |
Error-correcting signature code is proposed to identify users through a multiple-access adder channel. A $2^{j-1}$-dec... [more] |
IT2005-129 ISEC2005-186 WBS2005-143 pp.201-205 |
| LQE | 2005-12-09 11:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Digitally Tunable Laser Using Ladder Filter And Ring Resonator Shinji Matsuo, Seok-Hwan Jeong, Toru Segawa, Hiroshi Okamoto, Yoshihiro Kawaguchi, Yasuhiro Kondo, Hiroyuki Suzuki, Yuzo Yoshikuni (NTT Photonics Labs.) |
We have proposed and demonstrated the digitally tunable laser consisiting of the ladder filter and the ring resonator. T... [more] | LQE2005-115 pp.13-16 |
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