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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD | 2009-03-11 17:05 |
Okinawa | Fast Optimization on Minimum Perturbation Placement Realization Yuki Kouno, Yasuhiro Takashima (The Univ. of Kitakyushu), Atsushi Takahashi (Tokyo Inst. of Tech.)  VLD2008-137 |
[more] | VLD2008-137 pp.65-70 |
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| VLD | 2009-03-11 17:30 |
Okinawa | Delay Estimation of Sub-path under Path-delay Test Takanobu Shiki, Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC Corp.) VLD2008-138 |
[more] | VLD2008-138 pp.71-75 |
|
| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-29 13:45 |
Kanagawa | Circuit Partition Method with Time-multiplexed I/O Tatsuki Isomura (Univ. of Kitakyushu), Masato Inagi (Hiroshima City Univ.), Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC) VLD2008-100 CPSY2008-62 RECONF2008-64 |
We propose a partition method to prototype a large scaled system with time-multiplexed I/Os. Recent prototyping of a lar... [more] | VLD2008-100 CPSY2008-62 RECONF2008-64 pp.51-55 |
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| VLD | 2008-09-30 11:15 |
Ishikawa | Overlap-aware Analytical Placement Based on Stable-LSE Naoto Funatsu, Yasuhiro Takashima (Univ. of Kitakyushu) VLD2008-54 |
[more] | VLD2008-54 pp.43-48 |
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| VLD, CAS, SIP | 2008-06-27 10:55 |
Hokkaido | Hokkaido Univ. | Analytical Placement with Stable-LSE Naoto Funatsu, Yuta Ogomori, Yasuhiro Takashima (Univ. of Kitakyushu) CAS2008-24 VLD2008-37 SIP2008-58 |
[more] | CAS2008-24 VLD2008-37 SIP2008-58 pp.31-35 |
| VLD, IPSJ-SLDM | 2008-05-09 11:15 |
Hyogo | Kobe Univ. | Fast Wire Length Estimation in Obstructive Block Placement Shuting Li (Univ. of Kitakyushu), Tan Yan (Univ. of Illinois at Urbana-Champaign), Yasuhiro Takashima, Hiroshi Murata (Univ. of Kitakyushu) VLD2008-8 |
IP-reuse can enhance the design productivity only if the design methodology treats the IPs in a proper way. Especially i... [more] | VLD2008-8 pp.7-12 |
| CAS | 2008-02-01 09:25 |
Okinawa | A Post-Silicon Clock Tunig Method without Measuring the Variation Effects in Clock Signals Yuko Hashizume, Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC) CAS2007-95 |
In deep-submicron technologies, process variations can significantly affect the performance and yield of VLSI chips. Des... [more] | CAS2007-95 pp.7-12 |
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| CAS, SIP, VLD | 2007-06-22 13:40 |
Hokkaido | Hokkaido Tokai Univ. （Sapporo) | Optimization of Time-Multiplexed I/O Assignment in Multi-FPGA Systems Masato Inagi, Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC) CAS2007-28 VLD2007-44 SIP2007-58 |
Recently, integrated circuit design size and complexity have been increasing rapidly. FPGA systems are used to verify s... [more] |
CAS2007-28 VLD2007-44 SIP2007-58 pp.55-60 |
| VLD, IPSJ-SLDM | 2007-05-11 10:20 |
Kyoto | Kyodai Kaikan | A Clock Deskew Method using PDE with Discrete Delay Yuko Hashizume, Naoki Otani, Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC) VLD2007-9 |
In deep-submicron technology, process variations can severely affect the performance and the yield of VLSI chips. As a c... [more] | VLD2007-9 pp.13-18 |
| ICD, VLD | 2007-03-08 11:10 |
Okinawa | Mielparque Okinawa | A Clock Deskew Method Using Statisical Presumption Naoki Ootani, Yuko Hashizume, Yasuhiro Takashima (Univ. of Kitayushu), Yuichi Nakamura (NEC) |
In deep-submicron technology, process variations can severely affect the performance and the yield of VLSI chips. As a c... [more] | VLD2006-126 ICD2006-217 pp.43-48 |
| ICD, VLD | 2007-03-08 13:30 |
Okinawa | Mielparque Okinawa | Escape Fitting between a Pair of Pin-Sets Masato Inagi, Yasuhiro Takashima, Yoji Kajitani (Univ. of Kitakyushu) |
[more] | VLD2006-130 ICD2006-221 pp.67-72 |
| ICD, VLD | 2007-03-08 13:50 |
Okinawa | Mielparque Okinawa | BGA Routing by The Potential Router Takayuki Hiromatsu, Masato Inagi, Yasuhiro Takashima, Yoji Kajitani (Univ. of Kitakyushu) |
As the number of devices in an LSI chip becomes larger, the number of package pins also becomes larger. To fold the pins... [more] | VLD2006-131 ICD2006-222 pp.73-78 |
| ICD, VLD | 2007-03-08 14:30 |
Okinawa | Mielparque Okinawa | Relocation Method for Circuit Modification Kunihiko Yanagibashi, Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC) |
In this paper, we propose a novel migration method when the circuit with its placement is modified. In the method, its ... [more] | VLD2006-133 ICD2006-224 pp.85-90 |
| SIP, CAS, CS | 2007-03-06 09:30 |
Tottori | Blancart Misasa (Tottori) | [Poster Presentation]
A Fast Method for Analytical Placement Naoto Funatsu, Takumi Kurahara, Yasuhiro Takashima (Univ. of Kitakyushu) CAS2006-96 SIP2006-197 CS2006-113 |
[more] | CAS2006-96 SIP2006-197 CS2006-113 pp.19-21 |
| CAS | 2007-01-30 10:20 |
Ehime | Ehime Univ. | A Circuit Partitioning Algorithm for Multi-FPGA Systems with Time-multiplexed I/Os Masato Inagi, Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC) |
[more] | CAS2006-72 pp.13-17 |
| SIP, CAS, VLD | 2006-06-22 16:15 |
Hokkaido | Kitami Institute of Technology | Re-placement Method for Circuit Modification Kunihiko Yanagibashi, Yasuhiro Takashima (Univ. of Kitakyushu) |
This paper proposes a re-placement method for circuit modification．The re-placement is required to realize a placement w... [more] | CAS2006-7 VLD2006-20 SIP2006-30 pp.35-40 |
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