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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| IE, SIP, ICD, VLD, IPSJ-SLDM [detail] | 2012-10-19 14:55 |
Iwate | Hotel Ruiz | Fast Estimation of Dynamic Delay Distribution Dai Akita, Kenta Ando (Osaka Univ.), Atsushi Takahashi (Tokyo Tech.)  VLD2012-55 SIP2012-77 ICD2012-72 IE2012-79 |
As the improvement of digital circuits with fixed latency is about to reach its own limits, it is expected that variable... [more] | VLD2012-55 SIP2012-77 ICD2012-72 IE2012-79 pp.83-88 |
| ICD, SDM | 2012-08-02 15:15 |
Hokkaido | Sapporo Center for Gender Equality, Sapporo, Hokkaido | [Invited Talk]
STT-MRAM Development and Its Integration with BEOL Process for Embedded Applications Toshihiro Sugii, Yoshihisa Iba, Masaki Aoki, Hideyuki Noshiro, Koji Tsunoda, Akiyoshi Hatada, Masaaki Nakabayashi, Yuuichi Yamazaki, Atsushi Takahashi, Chikako Yoshida (LEAP) SDM2012-73 ICD2012-41 |
[more] | SDM2012-73 ICD2012-41 pp.55-58 |
| VLD | 2012-03-07 14:35 |
Oita | B-con Plaza | Performance of the Evaluation of a Variable-Latency-Circuit on FPGA Yuuta Ukon, Kenta Ando, Atsushi Takahashi (Osaka Univ) VLD2011-141 |
The performance of integrated circuits, which are the base of ICT nowaday, is always requested to be improved. In de f... [more] |
VLD2011-141 pp.127-132 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 10:05 |
Miyazaki | NewWelCity Miyazaki | A length difference reduction algorithm by using flow in set pair routing problem for single layer PCB routing Yusaku Yamamoto, Atsushi Takahashi (Osaka Univ.) VLD2011-87 DC2011-63 |
Recent advances in circuit speed forces to realize signal propagation delay accurately. In PCB routing design, desire... [more] |
VLD2011-87 DC2011-63 pp.203-208 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 10:30 |
Miyazaki | NewWelCity Miyazaki | An Improved Simulated Annealing for 3D Packing with Sequence Triple and Quintuple Representations Yiqiang Sheng (Tokyo Inst. of Tech.), Atsushi Takahashi (Osaka Univ.), Shuichi Ueno (Tokyo Inst. of Tech.) VLD2011-88 DC2011-64 |
The 3D packing for VLSI physical design is facing big challenges to get better solution quality with less computational ... [more] | VLD2011-88 DC2011-64 pp.209-214 |
| VLD | 2011-09-26 14:50 |
Fukushima | University of Aizu | MSA: Mixed Stochastic Algorithm for Placement with Larger Solution Space Yiqiang Sheng (Tokyo Inst. of Tech.), Atsushi Takahashi (Osaka Univ.), Shuichi Ueno (Tokyo Inst. of Tech.) VLD2011-42 |
The optimization techniques for VLSI/PCB placement with larger solution space and more objectives are facing big challen... [more] | VLD2011-42 pp.11-16 |
| MSS, CAS, VLD, SIP | 2011-07-01 14:30 |
Okinawa | Okinawa-Ken-Seinen-Kaikan | Performance Evaluation of Various Configurations of Adder in Error Detection/Correction Circuits Kenta Ando, Atsushi Takahashi (Osaka Univ.) CAS2011-26 VLD2011-33 SIP2011-55 MSS2011-26 |
The performance of a circuit is improved by introducing error detection/correction mechanism which uses the variation of... [more] | CAS2011-26 VLD2011-33 SIP2011-55 MSS2011-26 pp.147-152 |
| VLD | 2011-03-04 13:10 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | An evaluation of error detection/correction circuits by gate level simulation Masafumi Inoue (Tokyo Tech.), Yuuta Ukon, Atsushi Takahashi (Osaka Univ.) VLD2010-141 |
In a typical synchronous circuit design, the maximum delay between flip-flops gives a lower bound of the clock period su... [more] | VLD2010-141 pp.147-152 |
| VLD | 2011-03-04 13:35 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | Behavior Verification of a Variable Latency Circuit on FPGA Yuuta Ukon (Osaka Univ), Masafumi Inoue (Tokyo Tech), Atsushi Takahashi, Kenji Taniguchi (Osaka Univ) VLD2010-142 |
[more] | VLD2010-142 pp.153-158 |
| SDM | 2010-11-12 13:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
An overview of VLSI design automation and its future prospective Atsushi Takahashi (Osaka Univ.) SDM2010-179 |
Due to the continuous progress of VLSI manufacturing technology, the size of an element in VLSI becomes smaller and smal... [more] | SDM2010-179 pp.45-46 |
| VLD | 2010-09-27 17:00 |
Kyoto | Kyoto Institute of Technology | [Invited Talk]
Length Matching Routing on Single Layer for PCB Routing Design Yukihide Kohira (UoA), Atsushi Takahashi (Osaka Univ.) VLD2010-47 |
Due to the increase of operation frequency in recent LSI systems, signal propagation delays are required to achieve spec... [more] | VLD2010-47 pp.31-36 |
| VLD, IPSJ-SLDM | 2010-05-20 13:55 |
Fukuoka | Kitakyushu International Conference Center | An Efficient Congested Area Specification And Congestion Relaxation by 45 Degree Line for Single Layer Printed Circuit Board Rouitng Kyosuke Shinoda (Tokyo Tech), Yukihide Kohira (UoA), Atsushi Takahashi (Osaka Univ.) VLD2010-9 |
In recent VLSI systems, system performance increases while system size reduces. In Printed Circuit Board (PCB) design, ... [more] |
VLD2010-9 pp.79-84 |
| VLD | 2010-03-11 15:00 |
Okinawa | Fast Estimation Method of Peak Power considered Input Vector and Inner State of a Circuit Nobuyoshi Takahashi (Tokyo Inst. of Tech.), Yoichi Tomioka (Tokyo Univ. of Agriculture and Tech.), Yukihide Kohira (The Univ. of Aizu), Atsushi Takahashi (Osaka Univ.) VLD2009-115 |
The peak power of a clock synchronous circuit is requested to be small to reduce the influence on circuit performance an... [more] | VLD2009-115 pp.97-102 |
|
| VLD | 2010-03-11 16:05 |
Okinawa | Evaluation of a Detail Via Arrangement Method for 2-Layer Ball Grid Array Packages Masaki Kinoshita (Tokyo Inst. of Tech.), Yoichi Tomioka (Tokyo Univ. of Agr and Tech.), Atsushi Takahashi (Osaka Univ.) VLD2009-117 |
It takes a lot of time to obtain a routing design of the ball grid array (BGA) package which is one of LSI package, sinc... [more] | VLD2009-117 pp.109-114 |
|
| VLD | 2010-03-11 16:55 |
Okinawa | Clustering Method for Low Power Clock Tree in General Syncrhonous Framework Yukihide Kohira (Univ. of Aizu), Atsushi Takahashi (Osaka univ) VLD2009-119 |
In general synchronous framework, in which the clock is not assumed to be distributed to all registers simultaneously, t... [more] | VLD2009-119 pp.121-126 |
|
| VLD | 2010-03-12 10:25 |
Okinawa | Performance evaluation of ADDER with Error-Detection-Correction Mechanism Yuuta Ukon (Osaka Univ), Masafumi Inoue (Tokyo Inst. of Tech.), Atsushi Takahashi, Kenji Taniguchi (Osaka Univ) VLD2009-121 |
In complete-synchronous framework that is adopted as de facto standard in clock-synchronous circuit design, the maximum ... [more] | VLD2009-121 pp.133-137 |
|
| NS, IN (Joint) |
2010-03-04 09:20 |
Miyazaki | Miyazaki Phoenix Seagaia Resort (Miyazaki) | QoS Effect of Flow Control Scheme using Adaptive Receiving Opportunity Control for Wireless Multi-hop Networks Atsushi Takahashi, Nobuyoshi Komuro, Shiro Sakata, Shigeo Shioda (Chiba Univ.), Tutomu Murase (NEC) IN2009-146 |
In wireless multi-hop networks, network resource is greatly used due to the congestion by excessive inflow of low priori... [more] | IN2009-146 pp.13-18 |
| ICD | 2009-12-14 13:30 |
Shizuoka | Shizuoka University (Hamamatsu) | [Poster Presentation]
An evaluation of delay error rate of an adder in terms of clock period Yuuta Ukon, Atsushi Takahashi, Kenji Taniguchi (Osaka Univ.) ICD2009-91 |
Currently, digital circuits are mainly realized as synchronous circuits that uses global clocks. In clock-synchronous ci... [more] | ICD2009-91 pp.77-81 |
| SR, AN, USN (Joint) |
2009-10-22 11:30 |
Miyagi | Tohoku Univ. | Admission Control Scheme using Receiving Opportunity Control for Wireless Multi-hop Network Atsushi Takahashi, Nobuyoshi Komuro, Shiro Sakata, Shigeo Shioda (Chiba Univ.), Tutomu Murase (NEC Corp.) AN2009-26 |
QoS control is one of the most important issues of the wireless multi-hop networks. The authors previously proposed a pe... [more] | AN2009-26 pp.25-30 |
| VLD | 2009-09-24 13:55 |
Osaka | Osaka University | A Detail Via Arrangement Method for Reduction of Wire Congestion in 2-Layer Ball Grid Array Packages Masaki Kinoshita, Yoichi Tomioka (Tokyo Inst. of Tech.), Atsushi Takahashi (Osaka Univ.) VLD2009-30 |
A BGA package realizes a lot of connections between a chip and a printed board. The quality of routing design obtained ... [more] |
VLD2009-30 pp.7-12 |
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