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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| NLP, CAS | 2010-08-02 17:10 |
Tokushima | Naruto University of Education | [Invited Talk]
Some Problems on Nonlinear LC Circuits Hiroshi Kawakami  CAS2010-46 NLP2010-62 |
A simple LC circuit is defined as a fundamental oscillatory circuit, if it has no L(or C) only cut-set and L(or C) only ... [more] | CAS2010-46 NLP2010-62 pp.69-72 |
| MW | 2010-03-04 10:55 |
Kyoto | Ryukoku Univ. | A General Synthesis Method of Coupled Filter with Transmission Zeros Consist of Parallel Connected Lowpass Sectons Akiyoshi Inoue, Toshikazu Sekine, Yasuhiro Takahashi (Gifu Univ) MW2009-184 |
A general synthesis method of coupled filter with symmetrical or asymmetrical transmission zeros consist of parallel con... [more] | MW2009-184 pp.31-36 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-04 10:20 |
Kochi | Kochi City Culture-Plaza | A Study of two input LUT array type programmable logic architecture for cryptographic processing Ai Nakanishi, Kouta Ishibashi, Yuuichirou Kurokawa, Takeshi Fujino (Ritsumeikan Univ.) RECONF2009-49 |
Various kinds of block ciphers must be supported in order to communicate safely in computer networks by using the consum... [more] | RECONF2009-49 pp.49-54 |
| EMCJ, MW, IEE-MAG | 2009-10-23 11:50 |
Iwate | Iwate Univ. | A Synthesis Method of Coupled Filter with asymmetrical transmission zeros Consist of Parallel Connected Lowpass Sectons Akiyoshi Inoue, Toshikazu Sekine, Yasuhiro Takahashi (Gifu Univ) EMCJ2009-66 MW2009-115 |
A synthesis method of coupled filter with asymmetrical transmission zeros consist of parallel connected lowpass sectons ... [more] | EMCJ2009-66 MW2009-115 pp.129-134 |
| EMCJ, MW, IEE-MAG | 2009-10-23 14:00 |
Iwate | Iwate Univ. | A Reflection-Absorptive Band-Rejection Filter with a Dual-Band Wilkinson Power Divider
-- An Introduction of a Synthesis Tool for Wilkinson Power Divider -- Hiromitsu Uchida, Koji Yamanaka, Kazuhisa Yamauchi, Akira Inoue, Yoshihito Hirano, Moriyasu Miyazaki (Mitsubishi Electric Corp.) EMCJ2009-70 MW2009-119 |
Harmonic-termination technique is often introduced to RF high-power amplifiers in order to boost its efficiency. At the ... [more] | EMCJ2009-70 MW2009-119 pp.153-158 |
| ICD, ITE-IST | 2009-10-01 13:55 |
Tokyo | CIC Tokyo (Tamachi) | CMOS Analog Integrated Circuits for On-Chip Biosensing Kazuo Nakazato (Nagoya Univ.) ICD2009-42 |
New high-density and low-power CMOS analog integrated circuits, CMOS source-drain follower and CMOS source-measure unit,... [more] | ICD2009-42 pp.45-50 |
| MW | 2009-05-28 15:25 |
Okayama | Okayama Univ. | Synthesis/Design of Novel Ultra-Wideband Bandpass Filter Using Open-Ended Stub Loaded Parallel Coupled Three-Line Unit Chun-Ping Chen, Yoshinori Takakura, Hiroshige Nihei (Kanagawa Univ.), Zhewang Ma (Saitama Univ.), Tetsuo Anada (Kanagawa Univ.) MW2009-16 |
The purpose of this paper is to propose an effective design scheme to implement compact, high-performance wideband bandp... [more] | MW2009-16 pp.41-46 |
| VLD | 2009-03-11 16:15 |
Okinawa | A Delay Insertion Method for Clock Period Reduction with Fewer Delay Insertion in General-Synchronous Circuits Shuhei Tani, Yukihide Kohira, Atsushi Takahashi (Tokyo Inst. of Tech.) VLD2008-135 |
In general-synchronous framework, in which the clock is distributed periodically to each register but not necessarily si... [more] | VLD2008-135 pp.53-58 |
|
| SP | 2009-01-30 10:25 |
Nara | NAIST | Voice Synthesis Circuit Employing a Pulse Density based on Articulatory Model Hiroshi Kotaki, Jun Nonaka, Hakaru Tamukoh, Masatoshi Sekine (Tokyo Univ. of Agri & Tech) SP2008-133 |
Human various voices are made by a shape of a phonatory organ that changes its complexity with the muscles.In this paper... [more] | SP2008-133 pp.43-48 |
| EA | 2008-03-07 09:55 |
Tokyo | NTT Musashino R&D Center | Voice Synthesis Circuit with Pulse Density Kazushi Takahashi, Hiroshi Kotaki, Yuya Usami, Masatoshi Sekine (TUAT) EA2007-113 |
Human voice is sound made by the complex shapes and movement of vocal organ such as vocal cord, vocal tract, tongues an... [more] |
EA2007-113 pp.7-12 |
| VLD, ICD | 2008-03-06 11:35 |
Okinawa | TiRuRu | A Study for Implementation of High Speed Circuit Simulator by using FPGA Taiki Hashizume, Seiji Minoura, Tadashi Mizutani, Hironobu Ishijima, Shinichi Nishizawa (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Masahiro Fukui (Ritsumeikan Univ.) VLD2007-149 ICD2007-172 |
With recent advanced technology, simulation plays an important role in the design flow. However, the simulation requires... [more] | VLD2007-149 ICD2007-172 pp.31-36 |
| CAS | 2008-02-01 10:55 |
Okinawa | A Fast Modification Algorithm for Shortest Path Tree and its Performance Evaluation Tsutomu Ishida, Yukihide Kohira, Atsushi Takahashi (Tokyo Tech) CAS2007-98 |
In VLSI design, circuits are improved by circuit modifications.The minimum feasible clock period of a circuit is one of ... [more] | CAS2007-98 pp.25-30 |
|
| SIP, CAS, CS | 2007-03-06 09:30 |
Tottori | Blancart Misasa (Tottori) | [Poster Presentation]
Computation reduction in linear transform circuit synthesis using genetic algorithm Mai Suzuki, Takao Sasaki, Hisamichi Toyoshima (Kanagawa Univ.) CAS2006-97 SIP2006-198 CS2006-114 |
A linear transform circuit is often used in various transform such as DCT and DFT. In realizing in hardware, it is impor... [more] | CAS2006-97 SIP2006-198 CS2006-114 pp.23-27 |
| ICD, SIP, IE, IPSJ-SLDM | 2006-10-27 13:10 |
Miyagi | [Invited Talk]
General synchronous circuits using global clock
-- design methodologies, tools, and prospects -- Atsushi Takahashi (Tokyo Inst. of Tech.) |
In current VLSI design, most digital circuits are synthesized as synchronous circuits which are synchronized by global c... [more] | SIP2006-110 ICD2006-136 IE2006-88 pp.55-60 |
|
| RECONF | 2006-05-18 11:30 |
Miyagi | TOHOKU UNIVERSITY | A Retargetable Compiler for Cell-Array Based Self-Reconfigurable Architecture Masayuki Hiromoto, Shin'ichi Kouyama, Kentaro Nakahara, Hiroshi Tsutsui, Hiroyuki Ochi, Yukihiro Nakamura (Kyoto Univ.) |
Simulation-based quantitative performance evaluation using specific applications is indispensable for developing archite... [more] | RECONF2006-2 pp.7-12 |
| CAS | 2006-01-13 14:20 |
Miyazaki | A Transduction-based Framework to Synthesize RSFQ Circuits Shigeru Yamashita (NAIST), Katsunori Tanaka (NEC), Hideyuki Takada (Kyoto Univ.), Koji Obata, Kazuyoshi Takagi (Nagoya Univ.) |
In this paper, we propose a new framework to synthesize rapid single flux quantum (RSFQ) logic circuits. In our framewor... [more] | CAS2005-94 pp.43-48 |
|
| VLD, ICD, DC, IPSJ-SLDM | 2005-12-02 15:25 |
Fukuoka | Kitakyushu International Conference Center | Efficient contraction of timed signal transition graphs Tomohiro Yoneda (NII), Chris Myers (Univ. of Utah) |
In the decomposition based synthesis method, for each output signal, an input signal set sufficient to synthesize a cir... [more] |
VLD2005-86 ICD2005-181 DC2005-63 pp.59-64 |
| SCE | 2005-07-27 11:35 |
Aomori | Hirosaki Univ. | Automatic logic synthesis scheme and tool implementation for Single-Flux-Quantum circuits Yoshio Kameda, Shinichi Yorozu, Yoshihito Hashimoto (SRL) |
Single-flux-quantum (SFQ) logic circuits provide us a faster operation with low power consumption using Josephson juncti... [more] | SCE2005-17 pp.27-32 |
| CPSY, VLD, IPSJ-SLDM | 2005-01-26 14:40 |
Kanagawa | ASIP Architecture for Real-Time Graphical Effect Acceleration Tatsuhiro Yoshimura, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) |
Graphical effect processing realizes a variety of visual representation. In this paper, we propose an ASIP architectur... [more] |
VLD2004-118 CPSY2004-84 pp.49-54 |
|
| MSS, CAS | 2004-11-04 11:20 |
Aichi | Aichi Pref. Univ. | Arithmetic Cost Reduction Algorithm for Linear Transformation Circuits Considering the Synthesis Order of Coeficient Set Keisuke Sato, Takao Sasaki, Hisamichi Toyoshima (Kanagawa Univ.) |
For synthesis of linear transformation circuits, it is generally used that the coefficient matrix is partitioned i... [more] |
CAS2004-46 CST2004-25 pp.25-28 |
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