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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 41 - 60 of 119 [Previous]  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2016-02-17
10:25
Tokyo Kikai-Shinko-Kaikan Bldg. Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation
Fuqiang Li, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara (Kyutech) DC2015-87
Both logic paths and clock paths are subject to the impact of IR-Drop which occurs in capture mode during scan test. Thi... [more] DC2015-87
pp.7-12
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-01
15:45
Nagasaki Nagasaki Kinro Fukushi Kaikan [Fellow Memorial Lecture] Improving System Dependability by VLSI Test Technology
Seiji Kajihara (KIT) VLD2015-44 CPM2015-128 ICD2015-53 CPSY2015-64 DC2015-40 RECONF2015-51
VLSI Test technology for detection of manufacturing faults has been developed to improve test quality that is the capabi... [more] VLD2015-44 CPM2015-128 ICD2015-53 CPSY2015-64 DC2015-40 RECONF2015-51
pp.43-44(VLD), pp.9-10(CPM), pp.9-10(ICD), pp.19-20(CPSY), pp.43-44(DC), pp.19-20(RECONF)
IBISML 2015-11-27
14:00
Ibaraki Epochal Tsukuba [Poster Presentation] Nonnegative matrix factorization of test scores
Atsunori Kanemura (AIST), Hiroko Onari, Manabu Shikauchi, Masataka Hashimoto (Recruit Career), Shotaro Akaho (AIST) IBISML2015-80
When assessing skills of humans or designing itemsets, having fewer number of items is cost-efficient both in time and m... [more] IBISML2015-80
pp.203-208
MoNA 2015-08-04
14:35
Hyogo Kobe University Centennial Hall (Rokko Hall) [Encouragement Talk] How high is the floor? Floor Height Estimation Based on Mobile Phones with Sensor Data
Haruki Izumikawa, Yuki Hirota, Hiroshi Hanano, Chihiro Ono (KDDI Labs.) MoNA2015-12
We have undertaken research and development with the objectives of making cellular coverage distinctly visible and ident... [more] MoNA2015-12
pp.21-24
EMCJ, IEE-EMC, IEE-MAG 2015-06-26
11:00
Overseas KMITL, Thailand [Invited Talk] EMC Facilities for Products Certification for AEC
Kraison Aunchaleevarapan (PTEC, NSTDA, Thailand.) EMCJ2015-22
ASEAN Free Trade Area has set the standard of products to replace the existing tax measures. In this matter is enforce ... [more] EMCJ2015-22
p.33
DC 2015-02-13
16:00
Tokyo Kikai-Shinko-Kaikan Bldg An Evalution of a Fault Diagnosis Method for Single Logical Faults Using Multi Cycle Capture Test Sets
Hideyuki Takano, Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meiji Univ.) DC2014-86
Multi-cycle capture testing has been proposed to improve test quality of scan testing. However, fault diagnosis for mult... [more] DC2014-86
pp.49-54
IBISML 2014-03-07
11:35
Nara Nara Women's University Bayesian Test of Independence
Takanori Ayano, Joe Suzuki (Osaka Univ.) IBISML2013-77
This paper proposes Bayesian estimators of mutual information and independence tests.
Given independently emitted $n$ ... [more]
IBISML2013-77
pp.79-86
KBSE 2014-03-06
16:45
Okinawa Okinawaken-Seinenkaikan Equivalent Mutants Detection Method Using Symbolic Execution
Takaya Ueshiba, Weitao Wang, Hirohide Haga (Doshisha Univ.) KBSE2013-88
This paper proposes a method for automatically detecting equivalent mutants using symbolic execution. In mutation analys... [more] KBSE2013-88
pp.55-60
LOIS, ICM 2014-01-17
10:50
Nagasaki Nagasaki Museum of History and Culture Improving Exploratory Testing by Techniques for Visualizing Test Session Logs
Hajime Nakajima, Hidetaka Koya, Takeshi Masuda, Tsutomu Maruyama (NTT) ICM2013-43 LOIS2013-47
Testing which allows us to guarantee the quality of systems within the limited development time is one of the important ... [more] ICM2013-43 LOIS2013-47
pp.47-52
DC 2013-12-13
13:00
Ishikawa   Efficient Scan-Based BIST Architecture for Application-Dependent FPGA Test
Keita Ito, Tomokazu Yoneda, Yuta Yamato, Kazumi Hatayama, Michiko Inoue (NAIST) DC2013-68
This paper presents a scan-based BIST architecture for testing of application-dependent circuits configured on FPGA.
I... [more]
DC2013-68
pp.1-6
DC 2013-12-13
13:25
Ishikawa   Variable Test-Timing Generation for Built-In Self-Test on FPGA
Yasuo Sato, Munehiro Matsuura, Hitoshi Arakawa, Yousuke Miyake, Seiji Kajihara (Kyushu Inst. of Tech.) DC2013-69
This paper proposes a variable test-timing generation method that should be used for built-in self-test on FPGA. Applica... [more] DC2013-69
pp.7-12
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2013-11-29
09:45
Kagoshima   A Method of High Quality Transition Test Generation Using RTL Information
Hiroyuki Nakashima, Satoshi Ohtake (Oita Univ.) VLD2013-94 DC2013-60
With the miniaturization and high speed of large scale integrated circuits (VLSIs), it has become important to test dela... [more] VLD2013-94 DC2013-60
pp.239-244
SS, IPSJ-SE 2013-10-24
13:50
Ishikawa   A representation of relationships between functions and variables in source code
Yamato Takahashi, Kazuya Fukuhara, Toshimitsu Inomata, Yoshikazu Arai, Shintaro Imai (Iwate Prefectural Univ.) SS2013-40
In development of embedded software, the quality of software is very important.

A code review is performed in order ... [more]
SS2013-40
pp.49-54
CQ 2013-07-12
10:15
Hokkaido Hokkaido University 3D Video Quality Assessment Test in a Packet Loss Network
Takahiro Yamasaki, Takashi Nishi (OKI) CQ2013-23
3D video communication would be expected to enrich remote office communication. Usually, remote office communication car... [more] CQ2013-23
pp.55-60
NS, IN
(Joint)
2013-03-08
09:40
Okinawa Okinawa Zanpamisaki Royal Hotel QoE-based Log Collection in Minimization of Drive Tests
Haruki Izumikawa (KDDI Labs.), Ryuichi Yasunaga, Katsuhiro Kujirai, Shigeyuki Terachi, Yoshikazu Shirai (KDDI Engineering), Nao Kobayashi, Keizo Sugiyama (KDDI Labs.) NS2012-227
We have been conducting research into the creation of a coverage map or a map of coverage holes for mobile access system... [more] NS2012-227
pp.361-365
DC 2013-02-13
16:40
Tokyo Kikai-Shinko-Kaikan Bldg. Data volume reduction method for unknown value handling in built-in self test used in field
Yuta Yoshimi (NAIST), Kazumi Hatayama, Yuta Yamato, Tomokazu Yoneda, Michiko Inoue (NAIST/JST) DC2012-90
Many approaches on test pattern compression targeted unknown value handling. It is because unknown values have impacts o... [more] DC2012-90
pp.61-66
IN, IA
(Joint)
2012-12-14
08:55
Hiroshima Hiroshima City Univ. Stationarity Analysis and Prediction Model Construction of TCP Throughput by using Application-Level Mechanism
Hiroshi Yoshida, Kozo Satoda (NEC Corp.) IN2012-128
The end-to-end TCP throughput on best-effort networks, e.g., the Internet and mobile networks, fluctuates widely dependi... [more] IN2012-128
pp.39-44
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-28
16:00
Fukuoka Centennial Hall Kyushu University School of Medicine A Method to Estimate the Number of Don't-Care Bits with Netlist
Kohei Miyase, Seiji Kajihara, Xiaoqing Wen (KIT) VLD2012-104 DC2012-70
X-filling is often utilized so as to achieve test compression, test power reduction, or test quality improvement etc.
i... [more]
VLD2012-104 DC2012-70
pp.261-266
MW
(Workshop)
2012-08-08
- 2012-08-10
Overseas Chulalongkorn University, Bangkok, Thailand Evaluation of 5-GHz Band MIMO Communication Quality Under the Wireless Power Transmission Situation in a Spacecraft
Shuntaro Tashiro (Tokyo University of Science), Takumasa Noji (Tokyo Metropolitan University), Takako Kuroyanagi (Nihon Univ.), Goh Fukuda (Tokyo University of Science), Yuta Kobayashi, Satoshi Yoshida, Yusuke Maru, Yoshihiro Naruo, Shigeo Kawasaki (JAXA/ISAS)
Effects on multiple inputs multiple outputs (MIMO) communication quality from a wireless power transmission
(WPT) syste... [more]

CQ 2012-07-13
13:35
Ehime Ehime Univ. 3D Video Quality Assessment Test for Interoffice Communication
Takahiro Yamasaki, Takashi Nishi, Masato Nonaka (OKI) CQ2012-36
3D video communication would be expected to enrich remote office communication. Usually, remote office communication car... [more] CQ2012-36
pp.113-117
 Results 41 - 60 of 119 [Previous]  /  [Next]  
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