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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| TL | 2014-08-13 15:05 |
Tokyo | The University of Tokyo (Komaba) 18 Bldg. Hall | When high-capacity readers slow down and low-capacity readers speed up: Working memory differences in unbounded dependencies for German and Spanish readers Bruno Nicenboim, Pavel Logacev (Univ. of Potsdam), Carolina Gattei (IBYME), Shravan Vasishth (Univ. of Potsdam)  TL2014-33 |
We examined argument-head distance effects in SVO and SOV languages (Spanish and German) taking into account readers' wo... [more] | TL2014-33 pp.115-120 |
| ICD | 2014-04-17 12:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Design of Exchangeable MLC/TLC Hybrid Storage Array for Big Data Shogo Hachiya, Koh Johguchi (Chuo Univ.), Kousuke Miyaji (Shinshu Univ.), Ken Takeuchi (Chuo Univ.) ICD2014-5 |
A TLC-NAND flash provides a low cost and high capacity memory solution. However the reliability and access latency of TL... [more] | ICD2014-5 pp.21-26 |
| NC, MBE (Joint) |
2014-03-18 11:00 |
Tokyo | Tamagawa University | Active memory capacity in a neural network with short-term synaptic plasticity Kenji Tanaka (Univ. of Tokyo), Yasuhiko Igarashi (Univ. of Tokyo/JSPS), Masato Okada (Univ. of Tokyo/RIKEN) NC2013-105 |
In pre-frontal cortex (PFC), electro physiological experiments studies have established a link between the neuronal acti... [more] | NC2013-105 pp.97-102 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-29 13:20 |
Kagoshima | NoC routers using the marching memory through type Ryota Yasudo, Takahiro Kagami, Hideharu Amano (Keio Univ.), Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu (Renesas), Tadao Nakamura (Keio Univ.) CPSY2013-71 |
We propose a NoC(Network-on Chip) router using the marching memory through type in order to reduce the power consumption... [more] | CPSY2013-71 pp.71-76 |
|
| RECONF | 2013-09-19 14:15 |
Ishikawa | Japan Advanced Institute of Science and Technology | Development of Memory Management Framework for FPGA-based Prototyping Shinya Takamaeda-Yamazaki (Tokyo Inst. of Tech./JSPS Research Fellow), Kenji Kise (Tokyo Inst. of Tech.) RECONF2013-35 |
FPGA-based rapid prototyping supports faster emulation, but it requires the detailed implementation for each FPGA charac... [more] | RECONF2013-35 pp.91-96 |
| MRIS, ITE-MMS | 2013-07-12 15:45 |
Tokyo | Chuo Univ. | 3-Dimensional Phase Change Memory Enabling High Density and High Speed Storage Takashi Kobayashi, Masaharu Kinoshita, Yoshitaka Sasago (Hitachi) MR2013-11 |
A three-dimensional vertical chain-cell-type phase change memory (VCCPCM) for next-generation large-capacity storage was... [more] | MR2013-11 pp.31-34 |
| MRIS, ITE-MMS | 2013-03-08 17:05 |
Aichi | Nagoya Univ. | Study of current driven domain wall in CoB/Ni nanowire)
-- Basic research of magnetic nanowire memory -- Hiroyuki Awano, Duc The Ngo (Toyota Technological Inst.) MR2012-52 |
Warning that a shortage of storage as well as water and electricity by the rapid economic growth of emerging countries h... [more] | MR2012-52 pp.45-47 |
| IT, ISEC, WBS | 2013-03-07 15:05 |
Osaka | Kwansei Gakuin Univ., Osaka-Umeda Campus | Construction of Minimal dominating set for the Rank Modulation based on the Compressed Encoding Yuya Kanbayashi, Tomoharu Shibuya (Sophia Univ.) IT2012-79 ISEC2012-97 WBS2012-65 |
Rank Modulation code is a recoding code expressing information by using the mutual relation between the level of electri... [more] | IT2012-79 ISEC2012-97 WBS2012-65 pp.113-118 |
| VLD | 2013-03-05 15:35 |
Okinawa | Okinawa Seinen Kaikan | [Memorial Lecture]
Line Sharing Cache: Exploring Cache Capacity with Frequent Line Value Locality Keitarou Oka, Hiroshi Sasaki, Koji Inoue (Kyushu Univ.) VLD2012-151 |
This paper proposes a new last level cache architecture called line sharing cache (LSC), which can reduce the number of... [more] |
VLD2012-151 p.89 |
| TL | 2012-12-08 17:55 |
Tokyo | WASEDA University | Proficiency and Working Memory Effects on the Use of Animacy and Morphosyntactic Information in Comprehending Temporary Ambiguous Sentences by Japanese EFL Learners
-- An Eye-tracking Study -- Tomoyuki Narumi, Hirokazu Yokokawa (Kobe Univ.) TL2012-49 |
In this study, an eye-tracking experiment was conducted to investigate how Japanese EFL learners with intermediate profi... [more] | TL2012-49 pp.89-94 |
| CPSY | 2012-10-12 16:40 |
Hiroshima | Evaluation of memory management schema for Flash SSD Takuma Kouge, Toshiaki Kitamura (Hiroshima City Univ.) CPSY2012-43 |
The NAND Flash memory is nonvolatile semiconductor memory used for storage element of SSD. SSD needs to handle the data... [more] |
CPSY2012-43 pp.73-78 |
|
| IT | 2012-09-28 09:10 |
Gunma | Kusatsu Seminar House | Development of Generalized Encoder of BCH Code for Embedded System Nagamasa Mizushima, Yukihiro Takatani, Junji Ogawa, Atsushi Ishikawa (Hitachi) IT2012-36 |
For embedded systems that write data into flash memories at high speed, a parity of BCH code used for error correcting o... [more] | IT2012-36 pp.31-36 |
| CPM | 2012-09-25 15:30 |
Tokyo | 1Tbits/inch2 Recording in Angular-Multiplexing Holographic Memory Toshiki Ishii, Makoto Hosaka, Taku Hoshizawa (Hitachi), Asato Tanaka (MCRC) CPM2012-90 |
Angular-multiplexing holographic memory system is well known for its abilities of “Fast transfer rates” and “High densit... [more] | CPM2012-90 pp.25-27 |
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| ICD, SDM | 2012-08-02 15:55 |
Hokkaido | Sapporo Center for Gender Equality, Sapporo, Hokkaido | Scalable 3-D vertical chain-cell-type phase-change memory with 4F2 poly-Si diodes Masaharu Kinoshita, Yoshitaka Sasago, Hiroyuki Minemura, Yumiko Anzai, Mitsuharu Tai, Yoshihisa Fujisaki, Shuichi Kusaba, Tadao Morimoto, Takashi Takahama, Toshiyuki Mine, Akio Shima, Yoshiki Yonamoto, Takashi Kobayashi (Hitachi) SDM2012-74 ICD2012-42 |
A three-dimensional (3-D) vertical chain-cell-type phase-change memory (VCCPCM) for next-generation large-capacity stora... [more] | SDM2012-74 ICD2012-42 pp.59-63 |
| ICD | 2012-04-23 13:20 |
Iwate | Seion-so, Tsunagi Hot Spring (Iwate) | [Invited Talk]
128Gb 3-Bit Per Cell NAND Flash Memory on 19nm Technology with 18MB/s Write Rate Teruhiko Kamei, Yan Li, Seungpil Lee, Ken Oowada, Hao Nguyen, Qui Nguyen, Nima Mokhlesi, Cynthia Hsu, Jason Li, Venky Ramachandra, Masaaki Higashitani, Tuan Pham, Mitsuyuki Watanabe (SanDisk), Mitsuaki Honma, Yoshihisa Watanabe (Toshiba) ICD2012-2 |
A 128Gb 8-level NAND flash memory using 19nm CMOS technology has been developed. 128Gb is the largest single-chip capaci... [more] | ICD2012-2 pp.7-12 |
| ICD | 2012-04-23 15:10 |
Iwate | Seion-so, Tsunagi Hot Spring (Iwate) | [Invited Talk]
Dependable SSD design
-- The Issue for Enabling High Capacity Storage Device with Semiconductor -- Hiroshi Sukegawa (TOSHIBA) ICD2012-4 |
The increase of SSD storage capacity accompanies the total amount of circuit number increase of the memory chips embedde... [more] | ICD2012-4 pp.19-21 |
| ICD | 2012-04-24 10:50 |
Iwate | Seion-so, Tsunagi Hot Spring (Iwate) | A Non-Volatile Content Addressable Memory Using Three-Terminal Magnetic Domain Wall Motion Cells Ryusuke Nebashi, Noboru Sakimura, Yukihide Tsuji (NEC), Shunsuke Fukami (Tohoku Univ.), Hiroaki Honjo, Shinsaku Saito, Sadahiko Miura, Nobuyuki Ishiwata (NEC), Keizo Kinoshita, Takahiro Hanyu, Tetsuo Endoh, Naoki Kasai, Hideo Ohno (Tohoku Univ.), Tadahiko Sugibayashi (NEC) ICD2012-10 |
A 5-ns search operation of a non-volatile content addressable memory was demonstrated. The CAM macro, with a capacity of... [more] | ICD2012-10 pp.49-54 |
| MBE, NC (Joint) |
2012-03-14 16:50 |
Tokyo | Tamagawa University | Bayesian Network Associative Memories Hiroaki Hasegawa, Masafumi Hagiwara (Keio Univ.) NC2011-146 |
In this paper, we propose Bayesian Network Associative Memories (BNAMs) for modeling associative memories with Bayesian ... [more] | NC2011-146 pp.147-152 |
| IT, ISEC, WBS | 2012-03-01 16:10 |
Kanagawa | Construction of multiple error correcting WOM-Code Hidetoshi Utsunomiya, Hiroshi Kamabe (Gifu Univ.) IT2011-61 ISEC2011-88 WBS2011-62 |
Memory devices on which data can be written only once are called write once memories (WOM). A WOM code is a code which... [more] |
IT2011-61 ISEC2011-88 WBS2011-62 pp.95-100 |
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| NC | 2012-01-26 09:00 |
Hokkaido | Future University Hakodate | Storage capacity of the associative memory model with the zero-order synaptic decay Ryota Miyata (Tokyo Tech.), Jun Tsuzurugi (Okayama Univ. Sci.), Toru Aonishi (Tokyo Tech.), Koji Kurata (Univ. Ryukyu.) NC2011-97 |
It has been reported that synaptogenesis, formation of synaptic connection, continues to take place in certain regions o... [more] | NC2011-97 pp.1-6 |
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