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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 41 - 60 of 223 [Previous]  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF 2020-05-29
10:25
Online Online FPGA-based human motion estimation based on amalgamated data from multiple sensors
Xin Du, Yutaka Shinkai, Mizuki Itoh, Yoshiki Yamaguchi (Tsukuba Univ.) RECONF2020-12
This study proposes an FPGA-based system for identifying and estimating human motion by detecting data from sensors in d... [more] RECONF2020-12
pp.65-70
RECONF 2020-05-29
11:15
Online Online A study of fine-grained power supply adjustment with power packet on a local network
Siqing Wu, Yoshiki Yamaguchi (Tsukuba Univ) RECONF2020-14
Abstract Power packetization and its routing technology is the key technology in smart grid society because it enables ... [more] RECONF2020-14
pp.77-82
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2020-02-27
15:10
Kagoshima Yoron-cho Chuou-Kouminkan Accelerating Change-Point Detection on Multiple Multidimensional Stream Data using FPGA NIC
Takuma Iwata, Hiroki Matsutani (Keio Univ.) CPSY2019-94 DC2019-100
(To be available after the conference date) [more] CPSY2019-94 DC2019-100
pp.13-18
NLP, NC
(Joint)
2020-01-24
13:50
Okinawa Miyakojima Marine Terminal Ternarized Backpropagation for Edge AI and its FPGA Implementation
Tatsuya Kaneko, Yoshiharu Yamagishi, Hiroshi Momose, Tetsuya Asai (Hokkaido Univ.) NLP2019-95
In recent years there has been growing more interest in machine/deep learning.
As following this movement, many types ... [more]
NLP2019-95
pp.53-58
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-22
14:20
Kanagawa Raiosha, Hiyoshi Campus, Keio University Implementation and Evaluation of a Router on a Multi-FPGA System
Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Yugo Yamauchi, Kazuei Hironaka, Hideharu Amano (Keio Univ.) VLD2019-59 CPSY2019-57 RECONF2019-49
The trade-off between power efficiency and performance is important in large-scale computing systems like a datacenter. ... [more] VLD2019-59 CPSY2019-57 RECONF2019-49
pp.31-36
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-22
14:45
Kanagawa Raiosha, Hiyoshi Campus, Keio University Performance Evaluation of Using Multi-Switch on a Multi-FPGA System
Kohei Ito, Kensuke Iizuka, Yugo Yamauchi, Kazuei Hironaka (Keio Univ.), Yao Hu, Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) VLD2019-60 CPSY2019-58 RECONF2019-50
Flow-in-Cloud(FiC) is a system which consists of multiple middle-range FPGAs connected by high-speed serial links, and i... [more] VLD2019-60 CPSY2019-58 RECONF2019-50
pp.37-42
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-24
10:20
Kanagawa Raiosha, Hiyoshi Campus, Keio University Virtual-Channel Implementation on Communication Circuit of FPGA Cluster by Qsys Interconnect
Naohisa Fukase, Akihisa Furuiti, Yasuyuki Miura, Tsukasa-Pierre Nakao (SIT) VLD2019-82 CPSY2019-80 RECONF2019-72
In recent days, in order to improve the performance of computer, methods using FPGA have been attracting attention. FPGA... [more] VLD2019-82 CPSY2019-80 RECONF2019-72
pp.169-174
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2019-11-15
10:05
Ehime Ehime Prefecture Gender Equality Center Evaluation of operating performance of ECDSA hardware module
Yuya Takahashi, Monta kazuki (Kobe Univ.), Toshihiro Sato, Takaaki Okidono (ECSEC Lab), Takuji Miki, Noriyuki Miura, Makoto Nagata (Kobe Univ.) ICD2019-35 IE2019-41
There are limits to how much IoT power and encryption speed can be improved at the software level. Therefore, it is nece... [more] ICD2019-35 IE2019-41
pp.37-40
SR 2019-05-31
10:00
Tokyo Tokyo Big Sight [Technology Exhibit] QZSS short message SS-CDMA communication system -- Evaluation of transmitting timing control error --
Hiroshi Oguma, Rei Kawai, Takumi Shimada (NIT, Toyama), Takeshi Asai (Next-Dimension), Mizuki Motoyoshi, Suguru Kameda, Noriharu Suematsu (Tohoku Univ.) SR2019-12
We have proposed Spread Spectrum Code Division Multiple Access (SS-CDMA) short message communication
using Quasi-Zenith... [more]
SR2019-12
pp.71-77
NS 2019-05-16
09:45
Tokyo Kogakuin Univ. (Shinjuku Campus) [Encouragement Talk] Research on Scalability of DPDK Application by Utilizing FPGA NIC
Ikuo Otani, Yuki Akamatsu, Noritaka Horikome (NTT) NS2019-21
We are researching on performance improvement of SPP (Soft Patch Panel), which is high-speed DPDK software
connecting V... [more]
NS2019-21
pp.7-12
SC 2019-03-15
13:00
Tokyo National Institute of Informatics Study to achieve environment adaptive software
Yoji Yamato, Hirofumi Noguchi, Misao Kataoka, Takuma Isoda (NTT) SC2018-37
Recently, heterogeneous hardware such as GPU and FPGA is used in many systems and also IoT devices are increased repidly... [more] SC2018-37
pp.1-6
HWS, VLD 2019-02-27
17:10
Okinawa Okinawa Ken Seinen Kaikan Improvement on DMA Transfer Efficiency by Packet Concatenation
Shoko Ohteru, Saki Hatta, Tomoaki Kawamura, Koji Yamazaki, Takahiro Hatano, Akihiko Miyazaki, Koyo Nitta (NTT) VLD2018-106 HWS2018-69
(To be available after the conference date) [more] VLD2018-106 HWS2018-69
pp.79-84
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2019-01-30
13:30
Kanagawa Raiosha, Hiyoshi Campus, Keio University A CNN with a Noise Addition for Efficient Implementation on an FPGA
Atsuki Munakata, Shimpei Satou, Hiroki Nakahara (Tokyo Tech) VLD2018-75 CPSY2018-85 RECONF2018-49
This article is a technical report without peer review, and its polished and/or extended version may be published elsewh... [more] VLD2018-75 CPSY2018-85 RECONF2018-49
pp.19-24
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2019-01-31
09:55
Kanagawa Raiosha, Hiyoshi Campus, Keio University A Deduplication Mechanism for Effectively-once Semantics Using FPGA NIC
Koji Suzuki, Koya Mitsuzuka, Takuma Iwata, Hiroki Matsutani (Keio Univ.) VLD2018-83 CPSY2018-93 RECONF2018-57
(To be available after the conference date) [more] VLD2018-83 CPSY2018-93 RECONF2018-57
pp.65-70
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2019-01-31
14:00
Kanagawa Raiosha, Hiyoshi Campus, Keio University Preliminary evaluation of special instruction implementation methods by high level synthesis
Ryodai Iwamoto, Naoki Fujieda, Shuichi Ichikawa, Joji Sakamoto (TUT) VLD2018-88 CPSY2018-98 RECONF2018-62
Protection of intellectual properties and technical know-how is an important issue.In our previous work, we proposed imp... [more] VLD2018-88 CPSY2018-98 RECONF2018-62
pp.101-106
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2018-12-06
11:20
Hiroshima Satellite Campus Hiroshima An FPGA-NIC Based 40-Gbit/s Automated Response Circuit for Invalid DNS Packets to Suppress CPU Utilization of DNS Content Server
Shoko Ohteru, Saki Hatta, Tomoaki Kawamura (NTT), Koji Yamazaki (NTT-AT), Takahiro Hatano, Akihiko Miyazaki, Koyo Nitta (NTT) VLD2018-55 DC2018-41
(To be available after the conference date) [more] VLD2018-55 DC2018-41
pp.113-118
ASN, SRW
(Joint)
2018-11-05
13:00
Tokyo Tokyo Denki University, Tokyo Senju Campus [Poster Presentation] FPGA Implementation of Underwater Communication System used LED
Yuki Matsuda, Kei Miyagi, Chikatoshi Yamada, Shoichi Tanifuji (NIT,Okinawa College), Shuichi Ichikawa (TUT) ASN2018-61 SRW2018-26
Autonomous underwater robots are used for deep sea surveys.
acoustic communication was used for communication with the ... [more]
ASN2018-61 SRW2018-26
pp.43-46(ASN), pp.19-22(SRW)
SR 2018-10-30
10:30
Overseas Mandarin Hotel, Bangkok, Thailand [Poster Presentation] Transmitting Timing Calculation Unit with CPU on FPGA for QZSS Short Message SS-CDMA Communication
Hiroshi Oguma, Rei Kawai (NIT, Toyama), Takeshi Asai (Next Dimension Co. Ltd.), Mizuki Motoyoshi, Mizuki Motoyoshi, Suguru Kameda (Tohoku University) SR2018-60
We have proposed synchronized Spread-Spectrum Code-Division Multiple-Acc ess (SS-CDMA) communication for location and sh... [more] SR2018-60
pp.5-6
NS 2018-10-18
10:40
Kyoto Kyoto Kyoiku Bunka Center Research on Acceleration of DPDK Application by Utilizing FPGA
Ikuo Otani, Fumihiko Sawazaki, Noritaka Horikome (NTT) NS2018-106
We are researching on acceleration of SPP (Soft Patch Panel), which is high-speed DPDK software connecting VMs with phys... [more] NS2018-106
pp.7-12
RECONF 2018-09-17
16:25
Fukuoka LINE Fukuoka Cafe Space Accelerating Space Radiate Transfer on an FPGA
Tomoya Yokono, Norihisa Fujita, Yoshiki Yamaguchi, Yuuma Oobata, Ryohei Kobayashi, Taisuke Boku, Kohji Yoshikawa, Makito Abe, Masayuki Umemura (University of Tsukuba) RECONF2018-25
(To be available after the conference date) [more] RECONF2018-25
pp.35-40
 Results 41 - 60 of 223 [Previous]  /  [Next]  
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