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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 41 - 45 of 45 [Previous]  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD, SDM 2007-08-23
11:10		 Hokkaido Kitami Institute of Technology Multiphase-Output Level Shift System used in Multiphase PLL for Low Power Application
Akinori Matsumoto, Shiro Sakiyama, Yusuke Tokunaga, Takashi Morie, Shiro Dosho (Matsushita) SDM2007-146 ICD2007-74		 Low power design is essential for mobile application. For a PLL with multiphase outputs, level shifter (LS), which conve... [more] SDM2007-146 ICD2007-74
pp.29-34
ICD, SIP, IE, IPSJ-SLDM 2006-10-27
13:10		 Miyagi   [Invited Talk] General synchronous circuits using global clock -- design methodologies, tools, and prospects --
Atsushi Takahashi (Tokyo Inst. of Tech.) 		In current VLSI design, most digital circuits are synthesized as synchronous circuits which are synchronized by global c... [more] SIP2006-110 ICD2006-136 IE2006-88
pp.55-60
ICD, SDM 2006-08-17
17:25		 Hokkaido Hokkaido University An Ultra-Wide Range Digitally Adaptive Control Phase Locked Loop with New 3-Phase Switched Capacitor Loop Filter
Shiro Dosho, Naoshi Yanagisawa, Kazuaki Sogawa, Yuji Yamada, Takashi Morie (Matsushita Indusitrial Co. Ltd.) 		It is an innovative idea for modern PLL generation to control the bandwidth proportionally to a reference frequency. Rec... [more] SDM2006-141 ICD2006-95
pp.93-98
ICD, VLD 2006-03-09
11:30		 Okinawa   Improvement of Clustering Based Clock Scheduling Method
Yuuichi Sunahashiri, Yukihide Kohira, Atsushi Takahashi (Tokyo Tech) 		In order to achieve a shorter clock period by a clock tree with less wire length and less power consumption, a clusterin... [more] VLD2005-113 ICD2005-230
pp.31-36
MW, ED 2005-01-18
15:15		 Tokyo   A 10-Gbit/s CMOS burst-mode clock and data recovery IC for high-speed access networks
Shunji Kimura, Masafumi Nogawa, Kazuyoshi Nishimura, Tomoaki Yoshida, Kiyomi Kumozaki, Susumu Nishihara, Yusuke Ohtomo (NTT) 		We fabricated a 10-Gbit/s burst-mode clock and data recovery IC with a CMOS process for future high-speed access network... [more] ED2004-223 MW2004-230
pp.65-70
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