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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| NS | 2016-10-20 13:50 |
Hyogo | Himeji Nishi-Harima Area Jibasan Center | Distributed Packet Processing Architecture using Hardware Accelerators for 100Gbps Forwarding Throughput on Virtualized Edge Router Satoshi Nishiyama, Hitoshi Kaneko, Ichiro Kudo (NTT)  NS2016-90 |
To implement virtualized service edge functions on carrier networks by general-purpose servers, it is necessary to impro... [more] | NS2016-90 pp.13-18 |
| VLD | 2016-02-29 15:50 |
Okinawa | Okinawa Seinen Kaikan | ILP Based Synthesis of Soft-Error Tolerant Datapaths Considering Adjacency Constraint between Components Junghoon Oh, Mineo Kaneko (JAIST) VLD2015-116 |
As the device size decreases, the reliability degradation due to soft-errors is becoming one of the serious issues in VL... [more] | VLD2015-116 pp.31-36 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 09:20 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | A Handshake-delay-aware Scheduling Algorithm in High-level Synthesis for Four-phase Dual-rail Asynchronous Systems Kohta Itani, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2015-60 DC2015-56 |
This report is intended to discuss the scheduling problem in high-level synthesis~(HLS) for four-phase dual-rail asynchr... [more] | VLD2015-60 DC2015-56 pp.147-152 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 10:10 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | An Approach to Soft-Error Tolerant Datapath Synthesis Considering Adjacency Constraint between Components Junghoon Oh, Mineo Kaneko (JAIST) VLD2015-62 DC2015-58 |
As the device size decreases, the reliability degradation due to soft-errors is becoming one of the serious issues in VL... [more] | VLD2015-62 DC2015-58 pp.159-164 |
| SDM | 2015-11-06 13:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
GaN-based devices on Si substrates for power conversion systems Hidetoshi Ishida, Masahiro Ishida, Tetsuzo Ueda (Panasonic) SDM2015-90 |
GaN-based power devices have been expected to overcome the performance limit of conventional Si-based devices and enable... [more] | SDM2015-90 pp.35-38 |
| NLP | 2015-01-26 17:10 |
Oita | Compal Hall | The dependence to the active neuron's parameter of the searching performance for TSP's solutions by using DS-net Hikaru Okuda, Yoshihiro Hayakawa (NIT, Sendai) NLP2014-127 |
The Inverse function Delayed (ID) model has been proposed as one of the active neuron model. The ID model is expected as... [more] | NLP2014-127 pp.83-88 |
| CPSY, DC (Joint) |
2014-07-29 09:00 |
Niigata | Toki Messe, Niigata | Verification Method of the Split Circuit by High-Level Synthesis Tool in a Circuit Partitioning mechanism Kazuya Matsuda (TAT), Takefumi Miyoshi (e-trees.Japan), Masashi Takemoto (TAT), Satoshi Funada (e-trees.Japan), Hironori Nakajo (TAT) CPSY2014-17 |
In recent years, a high-level synthesis tool has been attracted in designing hardware circuits instead of traditional HD... [more] | CPSY2014-17 pp.43-48 |
| OFT | 2014-05-29 16:15 |
Yamagata | High Performance Polarization-Maintaining Optical Fiber Kazuyuki Hayashi, Katsuaki Izoe, Kazuhiko Aikawa, Manabu Kudoh (Fujikura) OFT2014-6 |
Two type of high performance polarization-maintaining optical fibers have been developed. First one is ultra bend-insens... [more] | OFT2014-6 pp.25-30 |
|
| VLD, IPSJ-SLDM | 2014-05-29 11:05 |
Fukuoka | Kitakyushu International Conference Center | Proposal of a Synthesis Flow for Asynchronous Circuits with Bundled-Data Implementation from a SystemC Model Taichi Komine, Hiroshi Saito (Univ. of Aizu) VLD2014-5 |
This paper proposes a synthesis flow for asynchronous circuits with bundled-data implementation from a SystemC model to ... [more] | VLD2014-5 pp.21-26 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 09:45 |
Kagoshima | An Area Constraint-Based Fault-Secure HLS Algorithm for RDR Architectures Considering Trade-Off between Reliability and Time Overhead Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-79 DC2013-45 |
With process technology scaling, decreasing reliability caused by soft errors as well as increasing the average intercon... [more] | VLD2013-79 DC2013-45 pp.129-134 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-29 11:40 |
Kagoshima | Clock Energy-efficient High-level Synthesis and Experimental Evaluation for HDR-mcd Architecture Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech./Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-97 DC2013-63 |
In this paper, we propose a clock energy-efficient high-level synthesis algorithm for HDR-mcd architecture. In HDR-mcd,... [more] |
VLD2013-97 DC2013-63 pp.263-268 |
|
| NLP | 2013-10-29 13:30 |
Kagawa | Sanport Hall Takamatsu | Discussion about the effectiveness of a DS-net and an active neuron model Yoshihiro Hayakawa, Hikaru Okuda (Sendai NCT.), Yuto Watanabe, Koji Nakajima (Tohoku Univ.) NLP2013-100 |
The active neuron model, which means an active region in output space, is an effective tool to avoid local minimum pro... [more] |
NLP2013-100 pp.159-164 |
| LQE, OPE | 2013-06-21 15:15 |
Tokyo | Push-Pull Modulation of Transverse Coupled-Cavity VCSELs Hamed Dalir, Fumio Koyama (Tokyo Inst. of Tech.) OPE2013-13 LQE2013-23 |
We propose the lateral coupled cavity VCSEL by using a bow-tie connection for enhancing the modulation bandwidth. Two ox... [more] | OPE2013-13 LQE2013-23 pp.33-38 |
|
| VLD, IPSJ-SLDM | 2013-05-16 16:00 |
Fukuoka | Kitakyushu International Conference Center | A Zero Time and Area Overhead Fault-Secure High-Level Synthesis Algorithm for RDR Architectures Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-9 |
In this paper, we propose a zero time and area overhead fault-secure high-level synthesis algorithm for RDR architecture... [more] | VLD2013-9 pp.67-72 |
| VLD | 2013-03-05 16:25 |
Okinawa | Okinawa Seinen Kaikan | [Memorial Lecture]
Network Simplex Method Based Multiple Voltage Scheduling in Power-Efficient High-Level Synthesis Cong Hao, Song Chen, Takeshi Yoshimura (Waseda Univ.) VLD2012-153 |
In this work, we focus on the problem of latencyconstrained scheduling with consideration of multiple voltage technolo... [more] |
VLD2012-153 pp.93-98 |
| ITE-BCT, IPSJ-AVM, CS, IE [detail] | 2012-12-07 09:55 |
Fukui | Fukuisi-chiiki-kouryu-plaza | High Accuracy Motion Estimation based on Gradient Method using Characteristics of High Frame-rate Images Yuki Sato, Danya Sugai, Takayuki Hamamoto (Tokyo Univ. of Science) CS2012-88 IE2012-102 |
In this paper, we propose a method of high accuracy motion estimation based on the gradient method by exploiting the cha... [more] | CS2012-88 IE2012-102 pp.101-106 |
| DC, CPSY (Joint) |
2012-08-03 09:00 |
Tottori | Torigin Bunka Kaikan | Implementation of the circuit division for High-Level Synthesis Daiki Kugami, Takaaki Miyajima, Hideharu Amano (Keio Univ.) CPSY2012-18 |
High-Level Synthesis has been researched and developed for these 20 years. Not only ASIC, but also reconfigurable devic... [more] |
CPSY2012-18 pp.55-60 |
| WBS | 2012-07-26 14:10 |
Aichi | Nagoya Univ. | Effect of Frame Length on Energy Minimization based on Adaptive LDPC Coded Modulation Kei Kinoshita, Hideki Ochiai (Yokohama National Univ.) WBS2012-24 |
In sensor networks, the wireless nodes are typically operated with small batteries for which their replacement is diffic... [more] | WBS2012-24 pp.79-83 |
| IPSJ-SLDM, VLD | 2012-05-30 15:45 |
Fukuoka | Kitakyushu International Conference Center | High-level Design Debugging Using Potential Dependence Shohei Ono, Takeshi Matsumoto, Masahiro Fujita (Univ. of Tokyo) VLD2012-4 |
As high-level design draws more attention and has been adopted more widely, verification and debugging for high- level d... [more] | VLD2012-4 pp.19-24 |
| ICD, IE, SIP, IPSJ-SLDM [detail] | 2011-10-25 15:55 |
Miyagi | Ｉｃｈｉｎｏｂｏ(Sendai) | Simultaneous Optimization of a CDFG Structure and a Schedule Based on Super-node Representation Akira Hirata, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) SIP2011-77 ICD2011-80 IE2011-76 |
In high-level synthesis, control-data flow graphs(CDFGs) are frequently used to describe the behavior of circuits since ... [more] | SIP2011-77 ICD2011-80 IE2011-76 pp.101-105 |
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