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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
ICD |
2013-04-12 15:55 |
Ibaraki |
Advanced Industrial Science and Technology (AIST) |
[Invited Lecture]
A 250MHz 18Mb Full Ternary CAM with 0.3V Match Line Sense Amplifier in 65nm CMOS Isamu Hayashi, Teruhiko Amano, Naoya Watanabe, Yuji Yano, Yasuto Kuroda, Masaya Shirata, Katsumi Dosaka, Koji Nii, Hideyuki Noda, Hiroyuki Kawai (Renesas Electronics) ICD2013-22 |
An 18Mb full ternary CAM with 0.3V match line sense amplifier (LV-MA) is designed and fabricated in 65nm bulk CMOS proce... [more] |
ICD2013-22 pp.115-120 |
CPSY |
2007-10-25 15:10 |
Kumamoto |
Kumamoto University |
Acceleration of Multimedia Data Processing with CAM-Enhanced Massive-Parallel SIMD Matrix Processor Takeshi Kumaki, Masakatsu Ishizaki, Masaharu Tagami, Tetsushi Koide, Hans Juergen Mattausch (Hiroshima Univ.), Takayuki Gyohten, Hideyuki Noda, Yasuto Kuroda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito (Renesas Technology) CPSY2007-27 |
A multimedia processor requires four capabilities, fast processing, small area size, low power consumption and programma... [more] |
CPSY2007-27 pp.19-24 |
ICD |
2007-04-12 14:20 |
Oita |
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A voltage scalable advanced DFM RAM with accelerated screening for low power SoC platform Hiroki Shimano, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto (Renesas Technology Corp.) ICD2007-8 |
The advanced-DFM (Design For Manufacturability) RAM provides the solution for the limitation of SRAM voltage scaling dow... [more] |
ICD2007-8 pp.41-46 |
ICD |
2007-04-13 11:00 |
Oita |
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[Invited Talk]
A high density embedded memory for Soc: Twin transistor RAM(TT-RAM) Kazutami Arimoto, Fukashi Morishita, Isamu Hayashi, Katsumi Dosaka (Renesas) ICD2007-13 |
A high speed/low power dissipation high density Twin transistor RAM(TT-RAM) has been developed as SOI CMOS platform memo... [more] |
ICD2007-13 pp.71-76 |
ICD, ITE-CE |
2006-12-15 12:05 |
Hiroshima |
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Multiple CAM Matches and Self-adapting Codeword Table for Optimized Real-time Huffman Encoding Masakatsu Ishizaki, Takeshi Kumaki, Yutaka Kono, Masaharu Tagami, Tetsushi Koide, Hans Juergen Mattausch (Hiroshima Univ.), Yasuto Kuroda, Takayuki Gyohten, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito (Renesas Technology Corp.) |
[more] |
ICD2006-165 pp.125-130 |
ICD, SDM |
2006-08-17 09:05 |
Hokkaido |
Hokkaido University |
A super parallel SIMD processor with Time/Space conversion Bus Bridge on the Matrix Architecture Tetsushi Tanizaki, Takayuki Gyohten, Hideyuki Noda, Masami Nakajima, Katsuya Mizumoto, Katsumi Dosaka (Renesas) |
A super parallel SIMD processor based on the matrix architecture which consists of 2k processors, embedded SRAM, and tim... [more] |
SDM2006-125 ICD2006-79 pp.1-6 |
ICD, VLD |
2006-03-10 15:35 |
Okinawa |
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An On-chip PVT Control System for Worst-caseless Lower Voltage SoC Design Takayuki Gyohten, Fukashi Morishita (Renesas Technology Corp.), Mako Okamoto (Daioh Electric Corp.), Katsumi Dosaka, Kazutami Arimoto (Renesas Technology Corp.) |
In this paper, we propose on-chip PVT (process, voltage, and temperature) control system for worst-caseless lower voltag... [more] |
VLD2005-132 ICD2005-249 pp.61-66 |
SIP, ICD, IE, IPSJ-SLDM |
2005-10-20 16:10 |
Miyagi |
Ichinobo, Sakunami-Spa |
A Soft-Error-Immune TCAM Archiecture with Associated Embedded DRAM Yuji Yano, Hideyuki Noda, Katsumi Dosaka, Fukashi Morishita, Kazunari Inoue, Toshiyuki Ogawa, Kazutami Arimoto (Renesas) |
[more] |
SIP2005-112 ICD2005-131 IE2005-76 pp.101-105 |
SIP, ICD, IE, IPSJ-SLDM |
2005-10-20 16:30 |
Miyagi |
Ichinobo, Sakunami-Spa |
A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI Takayuki Gyohten, Fukashi Morishita, Hideyuki Noda (Renesas Technology Corp.), Mako Okamoto (Daioh Electric Corp.), Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto (Renesas Technology Corp.) |
We propose a novel capacitorless twin-transistor random access memory (TTRAM). The 2Mb test device has been fabricated o... [more] |
SIP2005-113 ICD2005-132 IE2005-77 pp.107-112 |
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