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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2023-02-28 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg (Primary: On-site, Secondary: Online) |
A Seed Generation Method for Multiple Random Pattern Resistant Transition Faults for BIST Yangling Xu, Rei Miura, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (KSU)  DC2022-89 |
With shrinking feature sizes, growing clock frequencies, and decreasing power supply voltage, modern very large integrat... [more] | DC2022-89 pp.39-44 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2021-03-26 11:40 |
Online | Online | A Controller Augmentation method to Improving Transition Fault Coverage Kyohei Iizuka, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ) CPSY2020-63 DC2020-93 |
With shrinking feature sizes, growing clock frequencies, and decreasing power supply voltage, modern VLSIs are increasin... [more] | CPSY2020-63 DC2020-93 pp.79-84 |
| VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2019-11-14 15:20 |
Ehime | Ehime Prefecture Gender Equality Center | A Generation Method of Easily Testable Functional k Time Expansion Model for a Transition Fault Model Using Controller Augmentation and Partial Scan Designs Yuta Ishiyama, Toshinori Hosokawa, Yuki Ikegaya (Nihon Univ.) VLD2019-43 DC2019-67 |
One of the challenges on VLSI testing is to reduce the area overhead and test application time of design-for-testability... [more] | VLD2019-43 DC2019-67 pp.133-138 |
| VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2019-11-14 16:35 |
Ehime | Ehime Prefecture Gender Equality Center | Test Generation for Hardware Trojan Detection Using the Delay Difference of a Pair of Independent Paths Suguru Rikino, Yushiro Hiramoto, Satoshi Ohtake (Oita Univ.) VLD2019-46 DC2019-70 |
Hardware Trojan detection is important to ensure security of LSIs. If a hardware Trojan is inserted in a signal line o... [more] |
VLD2019-46 DC2019-70 pp.151-155 |
| DC | 2019-02-27 13:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | State Assignment Method to Improve Transition Fault Coverage for Datapath Masayoshi Yoshimura (Kyoto Sangyo Univ.), Yuki Takeuchi, Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ.) DC2018-78 |
Recently, it is indispensable to test in transition fault model due to timing defects increase along with complication a... [more] | DC2018-78 pp.43-48 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 14:30 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | A Method of LFSR Seed Generation for Improving Quality of Delay Fault BIST Kyonosuke Watanabe, Satoshi Ohtake (Oita Univ.) VLD2017-35 DC2017-41 |
With the miniaturization and high speed of large scale integrated circuits, it has become important to test delay faults... [more] | VLD2017-35 DC2017-41 pp.49-54 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-30 09:50 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | On SAT based test pattern generation for transition faults considering signal activities Yusuke Matsunaga (Kyushu Univ.) VLD2016-63 DC2016-57 |
This paper presents a test pattern generation method with considering signal transition activities using a SAT solver... [more] |
VLD2016-63 DC2016-57 pp.111-115 |
| VLD, CAS, MSS, SIP | 2016-06-16 10:30 |
Aomori | Hirosaki Shiritsu Kanko-kan | On random test pattern generation algorithm considering signal transition activities Yusuke Matsunaga (Kyushu Univ.) CAS2016-4 VLD2016-10 SIP2016-38 MSS2016-4 |
This paper presents a test pattern generation method with considering signal transition activities using Markov chain... [more] |
CAS2016-4 VLD2016-10 SIP2016-38 MSS2016-4 pp.19-22 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 10:05 |
Oita | B-ConPlaza | A Test Point Insertion Method to Reduce Capture Power Dissipation Yoshiyasu Takahashi, Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) VLD2014-99 DC2014-53 |
In at-speed scan testing of deep sub-micron era, high power dissipation can occur by high launch-induced switching activ... [more] | VLD2014-99 DC2014-53 pp.185-190 |
| DC | 2014-02-10 10:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Low Power Dissipation Oriented Don't Care Filling Method Using SAT Yoshiyasu Takahashi, Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ) DC2013-83 |
High power dissipation can occur by high launch-induced switching activity when the response to a test pattern is captur... [more] | DC2013-83 pp.25-30 |
| DC | 2014-02-10 16:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Low Power Consumption Oriented Test Generation Method for Transition Faults Using Multi Cycle Capture Test Generation Hiroshi Yamazaki, Yuto Kawatsure, Jun Nishimaki, Atsushi Hirai, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ), Koji Yamazaki (Meiji Univ) DC2013-89 |
High power dissipation can occur when the response to a test pattern is captured by flip-flops in at-speed scan testing,... [more] | DC2013-89 pp.61-66 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-29 09:45 |
Kagoshima | A Method of High Quality Transition Test Generation Using RTL Information Hiroyuki Nakashima, Satoshi Ohtake (Oita Univ.) VLD2013-94 DC2013-60 |
With the miniaturization and high speed of large scale integrated circuits (VLSIs), it has become important to test dela... [more] | VLD2013-94 DC2013-60 pp.239-244 |
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| DC | 2012-06-22 13:00 |
Tokyo | Room B3-1 Kikai-Shinko-Kaikan Bldg | An evaluation of a don't care filling method to improve fault sensitization coverage Ryosuke Wakasugi, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyusyu Univ) DC2012-9 |
A single stuck-at fault model and a transition fault model have been widely used to generate test patterns for VLSIs. Ho... [more] | DC2012-9 pp.1-6 |
| DC | 2012-02-13 11:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Pattern Merging for Additional Path Delay Fault Detection with Transition Delay Fault Test Hiroaki Tanaka, Kohei Miyase, Kazunari Enokimoto, Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2011-78 |
In this paper, we present to generate a test vector set to detect both transition and path delay faults. The proposed me... [more] | DC2011-78 pp.13-18 |
| DC | 2012-02-13 14:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A method to reduce the number of test patterns for transition faults using control point insertions Akihiko Takahashi, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ) DC2011-82 |
In recent year, the growing density and complexity for VLSIs cause an increase in the number of test patterns. Moreover,... [more] | DC2011-82 pp.37-42 |
| DC | 2011-02-14 11:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | An Analysis of Critical Paths for Field Testing with Process Variation Consideration Satoshi Kashiwazaki, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushuu Univ) DC2010-61 |
Recently, it has the problem that good VLSIs in production testing become defective VLSIs in the fields because small de... [more] | DC2010-61 pp.13-19 |
| DC | 2010-02-15 10:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Study on a Test Generation Method for Transition Faults Using Multi Cycle Capture Test Hiroshi Ogawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyusyu Univ.), Koji Yamazaki (Meiji Univ.) DC2009-67 |
Overtesting induces unnecessary yield loss. Untestable faults have no effect on normal functions of circuits. However, i... [more] | DC2009-67 pp.13-18 |
| DC | 2010-02-15 13:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Test Compaction Oriented Control Point Insertion Method for Transition Faults Yoshitaka Yumoto, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyusyu Univ.) DC2009-72 |
The recent advances in semiconductor processing technology have resulted in the exponential increase in LSI circuit dens... [more] | DC2009-72 pp.45-50 |
| DC | 2009-06-19 11:35 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Diagnositc Test Generation for Transition Faults Using a Stuck-at ATPG Tool Yoshinobu Higami, Yosuke Kurose, Satoshi Ohno, Hironori Yamaoka, Hiroshi Takahashi (Ehime Univ.), Yoshihiro Simizu, Takashi Aikyo (STARC), Yuzo Takamatsu (Ehime Univ.) DC2009-13 |
In modern high-speed LSIs, defects that cause timing failure occur often, and thus their detection and diagnosis are get... [more] | DC2009-13 pp.19-24 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-17 13:00 |
Fukuoka | Kitakyushu Science and Research Park | On Improving Transition Fault Coverage of Stuck-at Fault Tests Using Don't Care Identification Technique Kazumitsu Hamasaki, Toshinori Hosokawa (Nihon Univ.) VLD2008-60 DC2008-28 |
In recent year, transition fault testing and/or bridging fault testing for VLSIs are increasingly required in addition t... [more] | VLD2008-60 DC2008-28 pp.1-6 |
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