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Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF 2014-09-18
14:10		 Hiroshima   Prototype of fault tolerant FPGA using 65nm CMOS process
Motoki Amagasaki, Takuya Kajiwara, Kentaro Fujisawa, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2014-18		 我々はSoC（System on a Chip）に搭載されるFPGA-IP（Field Programmable Gate Array Intellectual
Property）コアに焦点をあてたFT-FPGA（Fault Tolera... [more]		 RECONF2014-18
pp.7-12
RECONF 2010-05-13
15:20		 Nagasaki   First Prototype Chip of a Non-Volatile Reconfigurable Logic using FeRAM Cells
Masahiro Koga, Masahiro Iida, Motoki Amagasaki (Kumamoto Univ.), Yoshinobu Ichida, Mitsuro Saji, Jun Iida (ROHM), Toshinori Sueyoshi (Kumamoto Univ.) RECONF2010-5		 An advantage of a RLD such as an FPGA is that it can be customized after being manufactured. However, there is a problem... [more] RECONF2010-5
pp.25-30
NS, PN
(Joint)		 2005-12-16
15:45		 Ehime   Development of 160 Gbit/s/port optical packet switch prototype based on narrow-band optical code label processing
Hideaki Furukawa, Naoya Wada, Tetsuya Miyazaki (NICT) 		We have developed optical packet switch prototype based on optical code label processing and optical buffering to improv... [more] PN2005-60
pp.75-80
ICD, CPM 2005-01-28
09:00		 Tokyo Kikai-Shinko-Kaikan Bldg. 10Gbps Serial Links Prototype for Server and Router
Masayoshi Yagyu, Hiroki Yamashita, Fumio Yuki, Tatsuya Kawasimo (CRL, Hitachi), Yasuhiro Hujimura (MDD, Hitachi), Yoshihumi Takada (ESD, Hitachi) 		This paper describes a trial production of 10Gbps class serial transmission prototype for servers and routers. Interfa... [more] CPM2004-162 ICD2004-207
pp.1-6
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