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Technical Committee on Image Engineering (IE) (Searched in: 2018)
Search Results: Keywords 'from:2018-12-05 to:2018-12-05'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-05 09:30 |
Hiroshima | Satellite Campus Hiroshima | Design Automation and Optimal Architecture of NLoC Yuto Umeda, Shigeru Yamashita (Ritsumeikan Univ.)  VLD2018-40 DC2018-26 |
In Networked Labs-on-Chip (NLoC), droplets of reagents flow in closed channels. It is expected that the discrete model... [more] |
VLD2018-40 DC2018-26 pp.1-6 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-05 09:55 |
Hiroshima | Satellite Campus Hiroshima | A Dynamic Programming Algorithm for Energy-aware Routing of Delivery Drones Yusuke Funabashi, Atsuya Shibata, Shunsuke Negoro (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2018-41 DC2018-27 |
[more] | VLD2018-41 DC2018-27 pp.7-11 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-05 10:20 |
Hiroshima | Satellite Campus Hiroshima | Prototyping of Real-time Computer-Aided Diagnosis System for Colorectal Endoscopic Movies and Images with Machine Learning Takumi Okamoto, Masayuki Odagawa, Koujiroh Takebayashi, Mikihisa Nagano, Tetsushi Koide, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda (Hiroshima Univ.), Shigeto Yoshida, Hiroshi Mieno (JR Hiroshima Hospital), Shinji Tanaka (Hiroshima Univ.), Takayuki Sugawara, Hiroshi Toishi, Masayuki Tsuji, Nobuo Tamba (Cadence, Japan) VLD2018-42 DC2018-28 |
In this paper, we discuss prototyping of real-time computer-aided diagnosis (CAD) system for colorectal endoscopic movie... [more] | VLD2018-42 DC2018-28 pp.13-18 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-05 09:55 |
Hiroshima | Satellite Campus Hiroshima | Development of Software/Hardware Cooperative System for Radiosity Method using High-Level Synthesis with an FPGA Kotaro Tamura, Tetsu Narumi (UEC univ.) RECONF2018-34 |
The calculation cost of a Radiosity method is huge, since it takes into account the global illumination to produce reali... [more] | RECONF2018-34 pp.1-6 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-05 10:20 |
Hiroshima | Satellite Campus Hiroshima | An FPGA implementation of Tri-state YOLOv2 using Intel OpenCL Youki Sada, Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara (titech) RECONF2018-35 |
Since the convolutional neural network has a high-performance recognition accuracy, it is expected to implement variou... [more] |
RECONF2018-35 pp.7-12 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-05 11:00 |
Hiroshima | Satellite Campus Hiroshima | [Keynote Address]
Challenge of Post CMOS Circuit Technologies for AI Hardware Takahiro Hanyu (Tohoku Univ.) |
Recently, it is impartant that the impact of artificial intelligence (AI) is being widely understood in several applicat... [more] | |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-05 13:00 |
Hiroshima | Satellite Campus Hiroshima | [Keynote Address]
Hiroki Nakahara (Titech) VLD2018-43 CPM2018-87 ICD2018-48 IE2018-66 CPSY2018-36 DC2018-29 RECONF2018-36 |
[more] | VLD2018-43 CPM2018-87 ICD2018-48 IE2018-66 CPSY2018-36 DC2018-29 RECONF2018-36 p.29(VLD), p.1(CPM), p.1(ICD), p.1(IE), p.1(CPSY), p.29(DC), p.13(RECONF) |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-05 14:15 |
Hiroshima | Satellite Campus Hiroshima | Basic Evaluation of Netlist Function Inference using GCN Hiroki Oyama, Motoki Amagasaki, Masahiro Iida (kumamoto Univ.), Hiroaki Yasuda, Hiroto Ito (MITSUBISHI ELECTRIC ENGINEERING) VLD2018-44 DC2018-30 |
In recent years, Recently GCN studies on graphs has been conducted.GCN is a kind of deep learning and classifies network... [more] | VLD2018-44 DC2018-30 pp.31-36 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-05 14:40 |
Hiroshima | Satellite Campus Hiroshima | Improved Routing Method for Two Layer Self-Aligned Double Patterning Shoya Tamura, Kunihiro Fujiyoshi (TUAT) VLD2018-45 DC2018-31 |
Self-Aligned Double Patterning (SADP) enables us to fabricate fine wiring under ArF immersion lithography. However, when... [more] | VLD2018-45 DC2018-31 pp.37-42 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-05 15:05 |
Hiroshima | Satellite Campus Hiroshima | Horizontal Wireless Bus for Free-Form SiP Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai (The Univ. of Tokyo) VLD2018-46 DC2018-32 |
We propose a wireless bus interface which connects chips integrated side by side wirelessly. Implementing large coils an... [more] | VLD2018-46 DC2018-32 pp.43-48 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 09:00 |
Hiroshima | Satellite Campus Hiroshima | Resources Utilization of Fine-grained Overlay Architecture Theingi Myint (Kumamoto), Qian Zhao (Kyutech), Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto) RECONF2018-37 |
This paper focuses on utilization of hardware resources for fine-grained overlay architecture. Overlay architectures inc... [more] | RECONF2018-37 pp.15-20 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 09:25 |
Hiroshima | Satellite Campus Hiroshima | Transparent Acceleration Method for Network Function Virtualization Using FPGA Yoshikazu Watanabe, Yuki Kobayashi, Takashi Takenaka, Baba Hiroshi (NEC) RECONF2018-38 |
Network Function Virtualization (NFV) is becoming a new networking architecture for telecom carriers. While NFV reali... [more] |
RECONF2018-38 pp.21-26 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 09:50 |
Hiroshima | Satellite Campus Hiroshima | An Evaluation of Acceleration Framework to Exploit TCAM implemented on FPGA Takefumi Miyoshi (WasaLab/e-trees.Japan), Satoshi Funada (e-trees.Japan) RECONF2018-39 |
[more] | RECONF2018-39 pp.27-31 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 09:00 |
Hiroshima | Satellite Campus Hiroshima | Stochastic Number Generation Considering Trade-off between Error and Overhead Yudai Sakamoto, Shigeru Yamashita (Ritsumeikan Univ.) VLD2018-47 DC2018-33 |
Stochastic Computing (SC) is an approximation calculation method using stochastic numbers (SNs) which represent the rati... [more] | VLD2018-47 DC2018-33 pp.65-70 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 09:25 |
Hiroshima | Satellite Campus Hiroshima | Quality determination of logic element placement using deep learning in fine grain reconfigurable device MPLD Hidehito Fujiishi, Tokio Kamada, Tetsuo Hironaka, Kazuya Tanigawa, Atsushi Kubota (Hiroshima city Univ.) VLD2018-48 DC2018-34 |
In CAD for MPLD which is a type of fine grain reconfigurable PLD, the SA method is used as a place-ment method for logic... [more] | VLD2018-48 DC2018-34 pp.71-76 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 09:50 |
Hiroshima | Satellite Campus Hiroshima | Secure PUF Authentication Method against Machine Learning Attack Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.) VLD2018-49 DC2018-35 |
It has been reported that the challenge and response authentication, which is a typical PUF authentication method, is vu... [more] | VLD2018-49 DC2018-35 pp.77-82 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 10:30 |
Hiroshima | Satellite Campus Hiroshima | Multi-FPGA implementation of deep learning applications Kazusa Musha, Akram Ben Ahmed (Keio Univ.), Kudoh Tomohiro (Univ. of Tokyo), Hideharu Amano (Keio Univ.) RECONF2018-40 |
FiC (Flow-in-Cloud) -SW is an FPGA-based switch board for deep learning applications. In this paper, we implemented a de... [more] | RECONF2018-40 pp.33-38 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 10:55 |
Hiroshima | Satellite Campus Hiroshima | A Tiny Memory implementation on an FPGA using Feature-Map Separable Convolution Technique Akira Jinguji, Simpei Sato, Hiroki Nakahara (titech) RECONF2018-41 |
Object detection and image recognition using a convolutional neural network (CNN) are used in embedded systems. Embedded... [more] | RECONF2018-41 pp.39-44 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 11:20 |
Hiroshima | Satellite Campus Hiroshima | Hardware implementation of ECG signals outlier detector trained by Sparse Robust Deep Autoencoder Naoto Soga, Shimpei Sato, Hiroki Nakahara (Titech) RECONF2018-42 |
Current ECG outlier detection is rule-based, there are many false positives, and it is necessary to study a new outlier ... [more] | RECONF2018-42 pp.45-50 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 10:30 |
Hiroshima | Satellite Campus Hiroshima | VLD2018-50 DC2018-36 |
[more] | VLD2018-50 DC2018-36 pp.83-88 |
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