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Technical Committee on Dependable Computing (DC)  (Searched in: 2013)

Search Results: Keywords 'from:2013-11-27 to:2013-11-27'
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Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Ascending)
 Results 41 - 60 of 72 [Previous]  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-28
09:20		 Kagoshima   A trade-off between hardware resources and detection accuracy for FPGA implementation of separability filters
Jimpei Hamamura, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) RECONF2013-48		 We propose three methods to reduce hardware resources required for FPGA implementation of separability filters and evalu... [more] RECONF2013-48
pp.51-56
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-28
10:00		 Kagoshima   ILP-Based Placement and Routing Method for PLDs for Minimizing Critical Path Length
Hiroki Nishiyama, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.) RECONF2013-49		 In this paper, we propose an ILP-based method for simultaneous optimal technology mapping, placement and routing for pro... [more] RECONF2013-49
pp.57-62
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-28
10:25		 Kagoshima   Automatic synthesis of the inter-processor communication implimentation for hetero multiprocessor systems
Yukihito Ishida, Yuki Ando, Shinya Honda, Hiroaki Takada, Masato Edahiro (Nagoya Univ.) RECONF2013-50		 This paper introduces an automatic synthesis technique of inter-processor communication for System-on-chip with heteroge... [more] RECONF2013-50
pp.63-68
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-28
11:05		 Kagoshima   [Invited Talk] Toward VLSI Reliability Enhancement by Reconfigurable Architecture
Takao Onoye, Masanori Hashimoto (Osaka Univ.), Yukio Mitsuyama (Kochi Univ. of Tech.), Dawood Alnajjar, Hiroaki Konoura (Osaka Univ.) VLD2013-87 CPM2013-122 ICD2013-99 CPSY2013-63 DC2013-53 RECONF2013-51		 Owing to wide spread of VLSI systems, a failure of the VLSIs may lead critical issue in our daily life. Especially in so... [more] VLD2013-87 CPM2013-122 ICD2013-99 CPSY2013-63 DC2013-53 RECONF2013-51
p.183(VLD), p.81(CPM), p.81(ICD), p.27(CPSY), p.183(DC), p.69(RECONF)
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-28
13:20		 Kagoshima   Real Chip evaluation of a low power reconfigurable accelerator with SOTB Technology
Hongliang Su, Hideharu Amano (Keio Univ.) RECONF2013-52		  [more] RECONF2013-52
pp.71-76
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-28
13:45		 Kagoshima   Evaluation of The First Flex Power FPGA chip with SOTB transistors
Chao Ma (AIST/Meiji Univ.), Masakazu Hioki (AIST), Takashi Kawanami (KIT), Yasuhiro Ogasahara, Tadashi Nakagawa, Toshihiro Sekigawa (AIST), Toshiyuki Tsutsumi (AIST/Meiji Univ.), Hanpei Koike (AIST) RECONF2013-53		 Flex Power FPGA was able to utilize a programmable threshold voltage to each circuit block of the FPGA by using the body... [more] RECONF2013-53
pp.77-82
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-28
14:10		 Kagoshima   Dependability-increasing demonstration of an optically differential reconfigurable gate array
Masato Seo, Minoru Watanabe (Shizuoka Univ.) RECONF2013-54		  [more] RECONF2013-54
pp.83-86
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-28
14:35		 Kagoshima   Architecture Evaluation Using The Place-and-Route Tool of a Reconstruction Device MPLD
Tomoya Yamashita, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Takashi Ishiguro (TAIYO YUDEN) RECONF2013-55		 In this paper, we evaluate some logic and interconnection structures for MPLD, which is a basic architecture
for reconf... [more]		 RECONF2013-55
pp.87-92
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-28
10:30		 Kagoshima   On Synthesis Algorithm for Parallel Index Generator Units
Yusuke Matsunaga (Kyushu Univ.) VLD2013-88 DC2013-54		 The index generation function is a multi-valued logic function which checks if the given input vector is a registered or... [more] VLD2013-88 DC2013-54
pp.203-208
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-28
10:55		 Kagoshima   A thermal analysis algorithm for VLSI chip by GPGPU
Takashi Ohmura, Lei Lin, Lin Meng, Masahiro Fukui (Ritsumeikan Univ.) VLD2013-89 DC2013-55		 In recent years, since the heat problem of the circuit accompanying high integration of the circuit is remarkable, therm... [more] VLD2013-89 DC2013-55
pp.209-214
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-28
11:20		 Kagoshima   List Scheduling Algorithms for Task Graphs with Data Parallelism
Yang Liu, Ittetsu Taniguchi, Hiroyuki Tomiyama, Lin Meng (Ritsumeikan Univ.) VLD2013-90 DC2013-56		  [more] VLD2013-90 DC2013-56
pp.215-220
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-28
13:20		 Kagoshima   Study of the Hardware Trojan for Embedded Processor
Yasushi Tsukada, Shuhei Itaya, Takeshi Kumaki (Ritsumeikan Univ.), Masaya Yoshikawa (Meijou Univ), Takeshi Fujino (Ritsumeikan Univ.) CPSY2013-64		 In recent years, much attention is paid to the threat and measure of LSI Hardware Trojan.
Hardware Trojan is the circui... [more]		 CPSY2013-64
pp.29-34
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-28
13:45		 Kagoshima   Implementation of a fast runtime visualization of a GPU-based electromagnetic simulation using a 3D-FDTD method
Kota Aoki, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri, Takafumi Fujimoto (Nagasaki Univ.) CPSY2013-65		 In this paper, we present implementation and evaluation of a fast runtime visualization of a GPU-based electromagnetic s... [more] CPSY2013-65
pp.35-40
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-28
14:10		 Kagoshima   TinyCSE: Tiny Computer System for Education
Ryosuke Nakamura, Koji Nakano, Yasuaki Ito (Hiroshima Univ.) CPSY2013-66		  [more] CPSY2013-66
pp.41-45
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-29
08:30		 Kagoshima   A Study of Burn-In Test Prediction by Data Mining
Satoshi Nonoyama, Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.), Yoshiyuki Nakamura (Renesas Electronics) VLD2013-91 DC2013-57		  [more] VLD2013-91 DC2013-57
pp.221-226
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-29
08:55		 Kagoshima   A Method of LFSR Seed Generation for Delay Fault BIST
Taro Honda, Satoshi Ohtake (Oita Univ.) VLD2013-92 DC2013-58		 In this paper, we propose a method to generate LFSR seeds for delay fault BIST. A conventional way to generate seeds is ... [more] VLD2013-92 DC2013-58
pp.227-231
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-29
09:20		 Kagoshima   Design and evaluation of circuits to control scan-in power in logic BIST
Takaaki Kato, Takeru Kina, Yousuke Miyake, Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.) VLD2013-93 DC2013-59		 Power reduction during Logic BIST is a crucial problem; however, power controlling technologies are required as well as ... [more] VLD2013-93 DC2013-59
pp.233-238
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-29
09:45		 Kagoshima   A Method of High Quality Transition Test Generation Using RTL Information
Hiroyuki Nakashima, Satoshi Ohtake (Oita Univ.) VLD2013-94 DC2013-60		 With the miniaturization and high speed of large scale integrated circuits (VLSIs), it has become important to test dela... [more] VLD2013-94 DC2013-60
pp.239-244
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-29
10:25		 Kagoshima   Forwarding Unit Generation for Loop Pipelining in High-Level Synthesis
Shingo Kusakabe, Tomohito Toyama, Kenshu Seto (Tokyo City Univ.) VLD2013-95 DC2013-61		 In the loop pipelining of high-level synthesis, the reduction of initiation intervals (IIs) is very important. Existing ... [more] VLD2013-95 DC2013-61
pp.245-249
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-29
11:15		 Kagoshima   Estimation for Method of Controller Implementation in High-Level Synthesis
Ryoya Sobue (Ritsumeikan Univ.), Yuko Hara-Azumi (NAIST), Ittetsu Taniguchi, Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2013-96 DC2013-62		  [more] VLD2013-96 DC2013-62
pp.257-262
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