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Technical Committee on Integrated Circuits and Devices (ICD) (Searched in: 2009)
Search Results: Keywords 'from:2009-12-14 to:2009-12-14'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2009-12-15 10:50 |
Shizuoka | Shizuoka University (Hamamatsu) | [Invited Talk]
History and Technology Trends of Si RF Analog LSI Developments
-- Emergence of New-Type Circuit Designers -- Tsuneo Tsukahara (Univ. of Aizu)  ICD2009-96 |
The history of silicon RF analog circuits is described, focusing on the development of CMOS RF circuits. Moreover, the e... [more] | ICD2009-96 pp.111-116 |
| ICD | 2009-12-15 13:30 |
Shizuoka | Shizuoka University (Hamamatsu) | A remote optically reconfigurable gate array with 4 configuration contexts Yumiko Ueno, Minoru Watanabe (Shizuoka Univ.) ICD2009-97 |
[more] | ICD2009-97 pp.117-120 |
| ICD | 2009-12-15 13:55 |
Shizuoka | Shizuoka University (Hamamatsu) | Wide Swing, Low Gain Error Voltage Buffer with Adaptive Biasing for Improving Slew-rate Jagatjyoti Ghimire, Cong-Kha Pham (The Univ. of Electro-comm.) ICD2009-98 |
An adaptively biased voltage buffer is proposed. Based on adaptive biasing, moderately high slew rate buffer has been im... [more] | ICD2009-98 pp.121-125 |
| ICD | 2009-12-15 14:20 |
Shizuoka | Shizuoka University (Hamamatsu) | Design of High Resolution Continuous-Time Bandpass Delta-Sigma AD Modulator Haijun Lin, Atushi Motozawa (Gunma Univ.), Pascal Lo Re, Kunihiko Iizuka (Sharp Corp.), Haruo Kobayashi (Gunma Univ.), Hao San (Tokyo City Univ.), Nobukazu Takai (Gunma Univ.) ICD2009-99 |
This paper describes the design and analysis of a high-resolution continuous-time bandpass ΔΣAD modulator for RF samplin... [more] | ICD2009-99 pp.127-132 |
| ICD | 2009-12-15 14:45 |
Shizuoka | Shizuoka University (Hamamatsu) | Sturdy-MASH-type ΔΣAD Modulator with Wide Dynamic Range Takafumi Yamada, Hajime Konagaya (Gunma Univ), Hao San (Tokyo City Univ), Haruo Kobayashi (Gunma Univ) ICD2009-100 |
This paper proposes a novel multi-stage noise shaping (MASH) architecture of ΔΣAD modulator which is robust against quan... [more] | ICD2009-100 pp.133-137 |
| ICD | 2009-12-15 15:10 |
Shizuoka | Shizuoka University (Hamamatsu) | Non-binary SAR ADC with Digital Compensation of Comparator Offset Effect Tomohiko Ogawa (Gunma Univ), Tatsuji Mtsuura (Renesas), Haruo Kobayashi, Nobukazu Takai (Gunma Univ), Masao Hotta, Hao San (Tokyo City Univ) ICD2009-101 |
This paper describes techniques for creating a low-power SAR ADC with an error-correcting non-binary successive approxim... [more] | ICD2009-101 pp.139-144 |
| ICD | 2009-12-15 15:45 |
Shizuoka | Shizuoka University (Hamamatsu) | A Simple High Efficiency DC-DC Converter Adaptive to Input Voltage and Load Current Pin Zhang, Cong-Kha Pham (The Univ. of Electro-Comm.) ICD2009-102 |
Even though the tendency is towards the suppression of power consumption in electronic devices, regulator circuits which... [more] | ICD2009-102 pp.145-149 |
| ICD | 2009-12-15 16:10 |
Shizuoka | Shizuoka University (Hamamatsu) | Inductor Design of 20-V Boost Converter for Low Power 3D Solid State Drive Tadashi Yasufuku, Koichi Ishida (Univ. of Tokyo.), Shinji Miyamoto, Hiroto Nakai (Toshiba), Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi (Univ. of Tokyo.) ICD2009-103 |
An inductor design for a 3D Solid State Drive (3D-SSD) with a boost converter are presented in this paper. The spiral in... [more] | ICD2009-103 pp.151-156 |
| ICD | 2009-12-15 16:35 |
Shizuoka | Shizuoka University (Hamamatsu) | Bandwidth Enhancement for TIA with Mutually Coupled Inductors Yoshihiro Okumura (Kyoto Univ.), Makoto Nakamura (NTT), Keiji Kishine (University of Shiga Prefecture), Akira Tsuchiya, Hidetoshi Onodera (Kyoto Univ.) ICD2009-104 |
A bandwidth enhancement technique for TransImpedance Amplifier (TIA) is proposed. Bandwidth is an important issue for C... [more] |
ICD2009-104 pp.157-161 |
| ICD | 2009-12-15 17:00 |
Shizuoka | Shizuoka University (Hamamatsu) | A 3D Processor Using Inductive-Coupling Inter-Chip Link
-- 3D System Integration of a 90nm CMOS Processor and a 65nm CMOS SRAM -- Kiichi Niitsu (Keio Univ./JST), Yasuhisa Shimazaki (Keio Univ./Renesas Technology), Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga (Keio Univ.), Itaru Nonomura (Renesas Technology), Makoto Saen, Shigenobu Komatsu, Kenichi Osada, Naohiko Irie (Hitachi), Toshihiro Hattori, Atsushi Hasegawa (Renesas Technology), Tadahiro Kuroda (Keio Univ.) ICD2009-105 |
A 90nm CMOS processor is mounted face down on a package by C4 bump and a 65nm CMOS 1MB SRAM is glued on it face up. The ... [more] | ICD2009-105 pp.163-168 |
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