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Technical Committee on Integrated Circuits and Devices (ICD) (Searched in: 2009)
Search Results: Keywords 'from:2009-12-14 to:2009-12-14'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2009-12-14 10:00 |
Shizuoka | Shizuoka University (Hamamatsu) | [Invited Talk]
Image Sensor
-- An absorbing device with the hardest design -- Satoshi Aoyama, Park Jong-Ho, Takashi Watanabe (Brookman Tech.), Shoji Kawahito (Brookman Tech./Shizuoka Univ.)  ICD2009-76 |
Many kinds of image sensors are used in various fields as for the key device of the image input, as well as other inform... [more] | ICD2009-76 pp.1-5 |
| ICD | 2009-12-14 10:50 |
Shizuoka | Shizuoka University (Hamamatsu) | [Invited Talk]
Experimental Evaluation Technique for Power Supply Noise and Logical Operation Failure Mitsuya Fukazawa (Renesas Technology Corp.), Makoto Nagata (Kobe Univ.) ICD2009-77 |
Logical operations in CMOS digital integration are highly prone to fail as the amount of power supply (PS) drop approach... [more] | ICD2009-77 pp.7-12 |
| ICD | 2009-12-14 13:30 |
Shizuoka | Shizuoka University (Hamamatsu) | [Poster Presentation]
Reducing pattern area technology of 3D transistor for system LSI Yu Hiroshima, Shigeyoshi Watanabe (Shonan Inst. of Tech.) ICD2009-78 |
We designed 1 bit Full Adder with FinFET, Double-Gate transistor. FinFET, Double-Gate transistor, Stacked type transisto... [more] | ICD2009-78 pp.13-18 |
| ICD | 2009-12-14 13:30 |
Shizuoka | Shizuoka University (Hamamatsu) | [Poster Presentation]
Design Technology of stacked NAND type MRAM Shouto Tamai, Shigeyoshi Watanabe (Shonan Inst. of Tech.) ICD2009-79 |
Design technology of stacked type MRAM using spin transistor has been described. Using 64 layer level cell structure fea... [more] | ICD2009-79 pp.19-23 |
| ICD | 2009-12-14 13:30 |
Shizuoka | Shizuoka University (Hamamatsu) | [Poster Presentation]
Design Technology of stacked NAND type 1-transistor FeRAM Koichi Sugano, Shigeyoshi Watanabe (Shonan Inst. of Tech) ICD2009-80 |
[more] | ICD2009-80 pp.25-29 |
| ICD | 2009-12-14 13:30 |
Shizuoka | Shizuoka University (Hamamatsu) | [Poster Presentation]
Simulation of Substrate Noise Impact on CMOS Analog Circuit Satoshi Takaya, Yoji Bando, Makoto Nagata (Kobe Univ.) ICD2009-81 |
We have measured and simulated substrate noise impact on basic analog amplifier using 90-nm CMOS test chip. To measure s... [more] | ICD2009-81 pp.31-34 |
| ICD | 2009-12-14 13:30 |
Shizuoka | Shizuoka University (Hamamatsu) | [Poster Presentation]
Modeling of power supply noise on CMOS digital circuits Daisuke Fujimoto, Tetsuro Matsuno, Makoto Nagata (Kobe Univ.) ICD2009-82 |
An arbitrary noise generator (ANG) is based on time-series charging of divided parasitic capacitance (TSDPC) and emulat... [more] |
ICD2009-82 pp.35-38 |
| ICD | 2009-12-14 13:30 |
Shizuoka | Shizuoka University (Hamamatsu) | [Poster Presentation]
Measurement and Simulation of Substrate Coupling of CMOS-RF Circuit Naoya Azuma, Makoto Nagata (Kobe Univ.) ICD2009-83 |
Susceptibility of radio frequency (RF) circuits against environmental noises was evaluated by way of direct power inject... [more] | ICD2009-83 pp.39-42 |
| ICD | 2009-12-14 13:30 |
Shizuoka | Shizuoka University (Hamamatsu) | [Poster Presentation]
Design Optimization of High-Speed, High-Gain OTA with gm/Id Lookup Table Method Takayuki Konishi, Shoichi Masui (Tohoku Univ.) ICD2009-84 |
We propose a design optimization flow for a gain-boosted folded-cascode operational transconductance amplifier, which ac... [more] | ICD2009-84 pp.43-48 |
| ICD | 2009-12-14 13:30 |
Shizuoka | Shizuoka University (Hamamatsu) | [Poster Presentation]
Ultra-Low Voltage 2-stage Amplifier Circuit with Wide Input/Output Range Ryosuke Takahashi, Tomochika Harada, Sumio Okuyama, Koichi Matsushita (Yamagata Univ.) ICD2009-85 |
In this paper, we present an ultra-low voltage 2-stage analog amplifier circuit using only subthreshold current. There ... [more] |
ICD2009-85 pp.49-53 |
| ICD | 2009-12-14 13:30 |
Shizuoka | Shizuoka University (Hamamatsu) | [Poster Presentation]
Process Variation Compensation Technique for 0.5-V Body-Input Comparator Jun Wang, Toshimasa Matsuoka, Kenji Taniguchi (Osaka Univ.) ICD2009-86 |
This work presents a compensation method for low-voltage body-input comparator to alleviate performance degradation due ... [more] | ICD2009-86 pp.55-56 |
| ICD | 2009-12-14 13:30 |
Shizuoka | Shizuoka University (Hamamatsu) | [Poster Presentation]
A Design of Parallel Analog-to-Digital Converter Utilizing Process Variations Hyunju Ham, Jun Wang, Toshimasa Matsuoka, Kenji Taniguchi (Osaka Univ.) ICD2009-87 |
[more] | ICD2009-87 pp.57-58 |
| ICD | 2009-12-14 13:30 |
Shizuoka | Shizuoka University (Hamamatsu) | [Poster Presentation]
A nanowatt DA converter for subthreshold CMOS LSIs Kazuki Yamamoto, Ken Ueno, Tetsuya Asai, Yoshihito Amemiya (Hokkaido Univ.) ICD2009-88 |
An ultra-low power digital-to-analog (DA) converter based on the technique of pulse-width-modulated DA conversion was pr... [more] | ICD2009-88 pp.59-64 |
| ICD | 2009-12-14 13:30 |
Shizuoka | Shizuoka University (Hamamatsu) | [Poster Presentation]
Intermittent Pulse Generator for Ultra-Low Power LSIs Hiromichi Matsushita, Ken Ueno, Tetsuya Asai, Yoshihito Amemiya (Hokkaido Univ.) ICD2009-89 |
We proposed a timer circuit for the intermittent operation of ultra-lowpower LSIs. The circuit consists of a clock oscil... [more] | ICD2009-89 pp.65-70 |
| ICD | 2009-12-14 13:30 |
Shizuoka | Shizuoka University (Hamamatsu) | [Poster Presentation]
A CMOS Image Sensor for Car-to-Car/Road-to-Car Optical Comunication Systems and evaluation Experiment of Communication Distance with LED Source of Light Moeta Hamai, Shinya Itoh, Md. Shakowat Zaman Sarker, Keita Yasutomi (Shizuoka Univ.), Isamu Takai, Michinori Andoh (TOYOTA Central R&D Labs..Inc.), Shoji Kawahito (Shizuoka Univ.) ICD2009-90 |
The optical communication system based on LED traffic lights or LED head/tail lights is presently being studied for the... [more] | ICD2009-90 pp.71-75 |
| ICD | 2009-12-14 13:30 |
Shizuoka | Shizuoka University (Hamamatsu) | [Poster Presentation]
An evaluation of delay error rate of an adder in terms of clock period Yuuta Ukon, Atsushi Takahashi, Kenji Taniguchi (Osaka Univ.) ICD2009-91 |
Currently, digital circuits are mainly realized as synchronous circuits that uses global clocks. In clock-synchronous ci... [more] | ICD2009-91 pp.77-81 |
| ICD | 2009-12-14 13:30 |
Shizuoka | Shizuoka University (Hamamatsu) | [Poster Presentation]
An Improved Face-Detection Method for a Massive-Parallel Memory-Embedded SIMD Matrix Processor MX-1 Hirokazu Hiramoto, Takeshi Kumaki, Yuta Imai, Tetsushi Koide, Hans Juergen Mattausch (Hiroshima Univ.) ICD2009-92 |
Recently, face-detection processing is more widely used in security applications, such as video surveillance system or e... [more] | ICD2009-92 pp.83-88 |
| ICD | 2009-12-14 13:30 |
Shizuoka | Shizuoka University (Hamamatsu) | [Poster Presentation]
Associative-Memory-Based LSI with Adaptive-Learning Capability Akio Kawabata, Wataru Imafuku, Tania Ansari, Hans Juergen Mattausch, Tetsushi Koide (Hiroshima Univ.) ICD2009-93 |
When pattern recognition is achieved by conventional techniques, processing time becomes long and it is difficult to de... [more] | ICD2009-93 pp.89-94 |
| ICD | 2009-12-14 13:30 |
Shizuoka | Shizuoka University (Hamamatsu) | [Poster Presentation]
Development of a Stream Cipher Engine Chip Takumi Ishihara, Harunobu Uchiumi, Yusuke Osumi, Masa-aki Fukase, Tomoaki Sato (Hirosaki Univ.) ICD2009-94 |
One of crucial points for next generation ubiquitous network is to keep the temporary security without relying on perman... [more] | ICD2009-94 pp.95-100 |
| ICD | 2009-12-15 10:00 |
Shizuoka | Shizuoka University (Hamamatsu) | [Invited Talk]
A New VLSI System Architecture Mimicking the Processing in the Mind Tadashi Shibata (Univ. of Tokyo.) ICD2009-95 |
The performance of a today’s computer is really marvelous. It can carry out a prodigious amount of numerical calculation... [more] | ICD2009-95 pp.101-109 |
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