| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
Technical Committee on Integrated Circuits and Devices (ICD) (Searched in: 2007)
Search Results: Keywords 'from:2007-08-23 to:2007-08-23'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD, SDM | 2007-08-24 11:35 |
Hokkaido | Kitami Institute of Technology | An analysis of asymmetry and orientation dependence of n-MOSFETs Toshihiro Matsuda, Yuya Sugiyama, Hideyuki Iwata (Toyama Pref. Univ.), Takashi Ohzone (Okayama Pref. Univ.)  SDM2007-161 ICD2007-89 |
n-MOSFETs with 8 different channel orientation and three kinds of process conditions were measured and symmetry of IDsat... [more] | SDM2007-161 ICD2007-89 pp.113-116 |
| ICD, SDM | 2007-08-24 13:00 |
Hokkaido | Kitami Institute of Technology | [Special Invited Talk]
Towards Great Nanoelectronics Country, Japan Hisatsune Watanabe (Selete) SDM2007-162 ICD2007-90 |
[more] | SDM2007-162 ICD2007-90 p.117 |
| ICD, SDM | 2007-08-24 13:50 |
Hokkaido | Kitami Institute of Technology | Design of High Density LSI with Three-Dimensional Transistor FinFET
-- Effect of Pattern Area Reduction with CMOS Cell Library -- Keisuke Okamoto, Keisuke Koizumi, Yu Hiroshima, Shigeyoshi Watanabe (SIT) SDM2007-163 ICD2007-91 |
New design method of system LSI with FinFET has been developed. Using planar+FinFET architecture the pattern area of CMO... [more] | SDM2007-163 ICD2007-91 pp.119-124 |
| ICD, SDM | 2007-08-24 14:15 |
Hokkaido | Kitami Institute of Technology | Ｄesign Method of system LSI with FinFET type DTMOS Yu Hiroshima, Shigeyoshi Watanabe, Keisuke Okamoto, Keisuke Koizumi (SIT) SDM2007-164 ICD2007-92 |
Planar DTMOS has a problem of increase of pattern area. Using FinFET type DTMOS excess pattern area of connect to gate a... [more] | SDM2007-164 ICD2007-92 pp.125-130 |
| ICD, SDM | 2007-08-24 14:50 |
Hokkaido | Kitami Institute of Technology | 0.7 V SRAM Technology with Stress-Enhanced Dopant Segregated Schottky (DSS) Source/Drain Transistors for 32 nm Node Hiroyuki Onoda, Katsura Miyashita, Takeo Nakayama, Tomoko Kinoshita, Hisashi Nishimura, Atsushi Azuma, Seiji Yamada, Fumitomo Matsuoka (Toshiba) SDM2007-165 ICD2007-93 |
For the fist time, low supply voltage SRAM operation with stress-enhanced dopant segregated Schottky (DSS) source/drain ... [more] | SDM2007-165 ICD2007-93 pp.131-134 |
| ICD, SDM | 2007-08-24 15:15 |
Hokkaido | Kitami Institute of Technology | SPRAM (SPin-transfer torque RAM) with a synthetic ferrimagnetic free layer for suppressing read disturbance and write-current dispersion Katsuya Miura, Takayuki Kawahara, Riichiro Takemura (Hitachi, Ltd.), Jun Hayakawa (Hitachi, Ltd./Tohoku Univ.), Michihiko Yamanouchi (Hitachi, Ltd.), Shoji Ikeda, Ryutaro Sasaki (Tohoku Univ.), Kenchi Ito, Hiromasa Takahashi, Hideyuki Matsuoka (Hitachi, Ltd.), Hideo Ohno (Tohoku Univ.) SDM2007-166 ICD2007-94 |
SPin-transfer torque RAM (SPRAM) with MgO-barrier-based magnetic tunnel junctions (MTJs) is a promising candidate for a ... [more] | SDM2007-166 ICD2007-94 pp.135-138 |
| ICD, SDM | 2007-08-24 15:40 |
Hokkaido | Kitami Institute of Technology | An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi (Kobe Univ.), Koji Nii (Kobe Univ./Renesas Technology), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) SDM2007-167 ICD2007-95 |
This paper demonstrates that an 8T memory cell can be alternative design to a 6T cell in a future highly-integrated SRAM... [more] | SDM2007-167 ICD2007-95 pp.139-144 |
| ICD, SDM | 2007-08-24 16:05 |
Hokkaido | Kitami Institute of Technology | A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues Satoshi Ishikura, M. Kurumada, Toshio Terano, Yoshinobu Yamagami, Naoki Kotani, Katsuji Satomi (Matushita Electric Industrial), Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Toshiyuki Oashi, Hiroshi Makino, Hirofumi Shinohara (Renesas Technology), Hironori Akamatsu (Matushita Electric Industrial) SDM2007-168 ICD2007-96 |
We propose a new 2port SRAM with a 8T single-read-bitline (SRBL) memory cell for 45nm SOCs. Access time tends to be slow... [more] | SDM2007-168 ICD2007-96 pp.145-148 |
| ICD, SDM | 2007-08-24 16:30 |
Hokkaido | Kitami Institute of Technology | A 128-Kbit, 16-Port SRAM Design with Multi-Stage-Sensing Scheme in 90-nm CMOS Technology Koh Johguchi, Yuya Mukuda, Shinya Izumi, Hans Juergen Mattausch, Tetsushi Koide (Hiroshima Univ.) SDM2007-169 ICD2007-97 |
[more] | SDM2007-169 ICD2007-97 pp.149-154 |
[Return to Top Page]