| Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
| ICD, SDM |
2006-08-18
10:15 |
Hokkaido |
Hokkaido University |
Suppression effects of threshold voltage variation with Ni FUSI gate electrode for 45nm node and beyond LSTP and SRAM devices
Yasunori Okayama, Tomohiro Saito, Aname Oishi, Kazuaki Nakajima, Kouji Matsuo, Syuichi Taniguchi, Takatoshi Ono, Kazuhiro Nakayama, Ryota Watanabe, Ayumi Eiho, Taiki Komoda, Taiki Kimura, Mssahumi Hamaguchi, Yoichi Takekawa, Tomonori Aoyama (TOSHIBA) |
[more] |
SDM2006-145 ICD2006-99
pp.115-120 |
| ICD, SDM |
2006-08-18
10:50 |
Hokkaido |
Hokkaido University |
[Special Invited Talk]
High Performance Dual Metal Gate CMOS with High Mobility and Low Threshold Voltage Applicable to Bulk CMOS Technology
Shinpei Yamaguchi, Kaori Tai, Tomoyuki Hirano, Takshi Ando, Susumu Hiyama, Junli Wang, Yoshiya Hagimoto, Yoshihiko Nagahama, Takayoshi Kato, Kaori Nagano, Mayumi Yamanaka, Sanae Terauchi, Saori Kanda, Ryo Yamamoto, Ｙａｓｕｓｈｉ Tateshita (STDG, SONY Corp.) |
[more] |
SDM2006-146 ICD2006-100
pp.121-126 |
| ICD, SDM |
2006-08-18
11:40 |
Hokkaido |
Hokkaido University |
Embedded Bulk FinFET SRAM Cell Technology with Planar FET Peripheral Circuit for hp32 nm node and beyond
Hirohisa Kawasaki (TAEC), Satoshi Inaba, Kimitoshi Okano, Akio Kaneko (Toshiba Semicon.), Atsushi Yagishita (TAEC), Takashi Izumida, Takahisa Kanemura, Takahiko Sasaki, Nobuaki Otsuka, Nobutoshi Aoki, Kyoichi Suguro, Kazuhiro Eguchi, Yoshitaka Tsunashima (Toshiba Semicon.), Kazunari Ishimaru (TAEC), Hidemi Ishiuchi (Toshiba Semicon.) |
[more] |
SDM2006-147 ICD2006-101
pp.127-132 |
| ICD, SDM |
2006-08-18
12:05 |
Hokkaido |
Hokkaido University |
A 65 nm Ultra-High-Density Dual-port SRAM with 0.71um2 8T-cell for SoC
Susumu Imaoka (Renesas Design), Koji Nii (Renesas Technology), Yasuhiro Masuda (Renesas Design), Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Motoshige Igarashi, Kazuo Tomita, Nobuo Tsuboi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology) |
We propose a new access scheme of synchronous dual-port (DP) SRAM that minimizes area of 8T-DP-cell and keeps cell stabi... [more] |
SDM2006-148 ICD2006-102
pp.133-136 |
| ICD, SDM |
2006-08-18
12:30 |
Hokkaido |
Hokkaido University |
A Stable SRAM Cell Design Against Simultaneously R/W Disturbed Accesses
Toshikazu Suzuki (Matsushita), Hiroyuki Yamauchi (Fukuoka Institute of Technology Univ.), Yoshinobu Yamagami, Katsuji Satomi, Hironori Akamatsu (Matsushita) |
A guarantee obligation of keeping the cell-margin against a simultaneously read and write (R/W) disturbed accesses in th... [more] |
SDM2006-149 ICD2006-103
pp.137-141 |
| ICD, SDM |
2006-08-18
13:45 |
Hokkaido |
Hokkaido University |
[Special Invited Talk]
Deep Pipelined SRAM Design for High Performance Processor
Toru Asano (IBM Japan) |
Processor performance depends strongly upon SRAM performance. In deep sub-micron technology, increasing device performan... [more] |
SDM2006-150 ICD2006-104
pp.143-147 |
| ICD, SDM |
2006-08-18
14:35 |
Hokkaido |
Hokkaido University |
A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits
Makoto Yabuuchi, Shigeki Ohbayashi, Koji Nii, Yasumasa Tsukamoto (Renesas Technology), Susumu Imaoka (Renesas Design), Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Hiroshi Makino, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology) |
[more] |
SDM2006-151 ICD2006-105
pp.149-153 |
| ICD, SDM |
2006-08-18
15:00 |
Hokkaido |
Hokkaido University |
A Vth-Variation-Tolerant SRAM with 0.3-V Minimum Operation Voltage for Memory-Rich SoC under DVS Environment
Hiroki Noguchi (Kobe Univ.), Yasuhiro Morita (Kanazawa Univ.), Hidehiro Fujiwara, Kentaro Kawakami, Junichi Miyakoshi (Kobe Univ.), Shinji Mikami (Kanazawa Univ.), Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) |
[more] |
SDM2006-152 ICD2006-106
pp.155-160 |
| ICD, SDM |
2006-08-18
15:25 |
Hokkaido |
Hokkaido University |
Impact of Random Telegraph Signals on Scaling of Multilevel Flash Memories
Hideaki Kurata, Kazuo Otsuga, Akira Kotabe, Shinya Kajiyama, Taro Osabe, Yoshitaka Sasago (Hitachi), Shunichi Narumi, Kenji Tokami, Shiro Kamohara, Osamu Tsuchiya (Renesas) |
This paper describes for the first time the observation of the threshold voltage (Vth) fluctuation due to random telegra... [more] |
SDM2006-153 ICD2006-107
pp.161-166 |
|