Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
SDM, ICD |
2013-08-01 09:00 |
Ishikawa |
Kanazawa University |
Analysis of Steep Subthreshold Slope Characteristics in SOI MOSFET Takayuki Mori, Jiro Ida (Kanazawa Inst. of Tech.) SDM2013-65 ICD2013-47 |
We have found out that the steep Subthreshold Slope (SS) appears in the Floating-Body (FB) and the Body-Tied (BT) SOI MO... [more] |
SDM2013-65 ICD2013-47 pp.1-6 |
SDM, ICD |
2013-08-01 09:25 |
Ishikawa |
Kanazawa University |
Performance Enhancement of Tunnel Field-Effect Transistors by Synthetic Electric Field Effect Yukinori Morita, Takahiro Mori, Shinji Migita, Wataru Mizubayashi, Akihito Tanabe, Koichi Fukuda, Kazuhiko Endo, Takashi Matsukawa, Shin-ichi O'uchi, Yongxun Liu, Meishoku Masahara, Hiroyuki Ota (AIST) SDM2013-66 ICD2013-48 |
A synthetic electric field effect to enhance the performance of tunnel field-effect transistors (TFETs) is proposed. The... [more] |
SDM2013-66 ICD2013-48 pp.7-12 |
SDM, ICD |
2013-08-01 09:50 |
Ishikawa |
Kanazawa University |
Scaling Strategy for Low Power RF Applications with Multi Gate Oxide Dual Work function (DWF) MOSFETs Utilizing Self-Aligned Integration Scheme Toshitaka Miyata, Shigeru Kawanaka, Akira Hokazono, Tatsuya Ohguro, Yoshiaki Toyoshima (TOSHIBA) SDM2013-67 ICD2013-49 |
Dual Work Function (DWF)-MOSFET of 100 nm gate length device with self-aligned integration scheme was demonstrated utili... [more] |
SDM2013-67 ICD2013-49 pp.13-18 |
SDM, ICD |
2013-08-01 10:25 |
Ishikawa |
Kanazawa University |
[Invited Talk]
Future of Integrated Circuit R&D: Grow out from Parts/Component Mind Kazuya Masu (Tokyo Inst. of Tech.) SDM2013-68 ICD2013-50 |
[more] |
SDM2013-68 ICD2013-50 pp.19-22 |
SDM, ICD |
2013-08-01 11:10 |
Ishikawa |
Kanazawa University |
[Invited Talk]
3D-architecture technology movements and opportunity of Japan Hiroaki Ikeda (ASET) SDM2013-69 ICD2013-51 |
This is the overview of the world wide TSV/3D integration technology developments and State of the Art in Japan. Latter... [more] |
SDM2013-69 ICD2013-51 pp.23-28 |
SDM, ICD |
2013-08-01 13:00 |
Ishikawa |
Kanazawa University |
[Invited Talk]
Tera-Scale Three-Dimensional Integration (3DI) using Bumpless TSV Interconnects Takayuki Ohba (Tokyo Inst. of Tech.) SDM2013-70 ICD2013-52 |
In combination with 3D logic, memory, and cooling devices, it is possible to construct a roadmap towards high-density in... [more] |
SDM2013-70 ICD2013-52 pp.29-30 |
SDM, ICD |
2013-08-01 13:45 |
Ishikawa |
Kanazawa University |
[Invited Talk]
Design and diagnosis of 100GB/s Wide I/O with 4096b TSVs through Active Silicon Interposer Makoto Nagata, Satoshi Takaya (Kobe Univ.), Hiroaki Ikeda (ASET) SDM2013-71 ICD2013-53 |
A 4096-bit wide I/O bus structure is designed and demonstrated with a three dimensional chip stack incorporating memory,... [more] |
SDM2013-71 ICD2013-53 pp.31-34 |
SDM, ICD |
2013-08-01 14:40 |
Ishikawa |
Kanazawa University |
[Invited Talk]
A 0.15mm-Thick Non-Contact Connector for MIPI Using Vertical Directional Coupler Atsutake Kosuge, Wataru Mizuhara, Tsunaaki Shidei, Tsutomu Takeya, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda (Keio Univ.) SDM2013-72 ICD2013-54 |
The world's first 0.15-mm-thick non-contact connector for Mobile Industry Processor Interface (MIPI) applications is pre... [more] |
SDM2013-72 ICD2013-54 pp.35-40 |
SDM, ICD |
2013-08-01 15:40 |
Ishikawa |
Kanazawa University |
[Panel Discussion]
3D Integration: What and when do we expect? Kazuya Masu (Tokyo Inst. of Tech.), Hiroaki Ikeda (ASET), Makoto Nagata (Kobe Univ), Kenji Takahashi (Toshiba), Takayuki Ohba (Tokyo Inst. of Tech.), Daisuke Suzuki (Pezy Computing) SDM2013-73 ICD2013-55 |
[more] |
SDM2013-73 ICD2013-55 p.41 |
SDM, ICD |
2013-08-02 09:00 |
Ishikawa |
Kanazawa University |
SRAM Cell Stability Parameter: Noise Margin or Vmin? Anil Kumar, Takuya Saraya (Univ. of Tokyo), Shinji Miyano (STARC), Toshiro Hiramoto (Univ. of Tokyo) SDM2013-74 ICD2013-56 |
This paper reports the comprehensive analysis of the stability parameter of SRAM cells. Results show that even if noise ... [more] |
SDM2013-74 ICD2013-56 pp.43-46 |
SDM, ICD |
2013-08-02 09:25 |
Ishikawa |
Kanazawa University |
Reduced Cell Current Variability in Fully Depleted Silicon-on-Thin-BOX (SOTB) SRAM Cells at Supply Voltage of 0.4V Tomoko Mizutani (Univ. of Tokyo), Yoshiki Yamamoto, Hideki Makiyama, Hirofumi Shinohara, Toshiaki Iwamatsu, Hidekazu Oda, Nobuyuki Sugii (LEAP), Toshiro Hiramoto (Univ. of Tokyo) SDM2013-75 ICD2013-57 |
Cell current (ICELL) variability in 6T-SRAM composed of silicon-on-thin-BOX (SOTB) MOSFETs by 65nm technology is measure... [more] |
SDM2013-75 ICD2013-57 pp.47-52 |
SDM, ICD |
2013-08-02 09:50 |
Ishikawa |
Kanazawa University |
A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Yasumasa Tsukamoto, Yuichiro Ishii (Renesas Electronics), Tetsuya Matsumura (Nihon Univ.), Yoshio Matsuda (Kanazawa Univ.) SDM2013-76 ICD2013-58 |
[more] |
SDM2013-76 ICD2013-58 pp.53-57 |
SDM, ICD |
2013-08-02 10:25 |
Ishikawa |
Kanazawa University |
28nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique Yukiko Umemoto, Koji Nii, Jiro Ishikawa, Makoto Yabuuchi, Yasumasa Tsukamoto, Shinji Tanaka, Koji Tanaka, Kazutaka Mori, Kazumasa Yanagisawa (Renesas Electronics) SDM2013-77 ICD2013-59 |
We propose a new 2T mask read only memory (ROM) with dynamic column source bias control technique, which enables achievi... [more] |
SDM2013-77 ICD2013-59 pp.59-64 |
SDM, ICD |
2013-08-02 10:50 |
Ishikawa |
Kanazawa University |
A 123uW Standby Power Technique with EM-Tolerant 1.8V I/O NMOS Power Switch in 28nm HKMG Technology Kazuki Fukuoka, Ryo Mori, Akira Kato, Mitsuhiko Igarashi, Koji Shibutani, Takashi Yamaki, Koji Nii, Sadayuki Morita, Takao Koike (Renesas Electronics), Noriaki Sakamoto (Renesas Mobile) SDM2013-78 ICD2013-60 |
[more] |
SDM2013-78 ICD2013-60 pp.65-69 |
SDM, ICD |
2013-08-02 11:15 |
Ishikawa |
Kanazawa University |
[Invited Talk]
An LDPC Decoder with Time Domain Analog and Digital Mixed Signal Processing Daisuke Miyashita, Ryo Yamaki (Toshiba), Kazunori Hashiyoshi (Toshiba Microelectronics), Hiroyuki Kobayashi, Shouhei Kousai, Yukihito Oowaki, Yasuo Unekawa (Toshiba) SDM2013-79 ICD2013-61 |
Analog computation is potentially more efficient in certain arithmetic operations since a single wire can represent mult... [more] |
SDM2013-79 ICD2013-61 pp.71-76 |
SDM, ICD |
2013-08-02 13:00 |
Ishikawa |
Kanazawa University |
A 0.4-1V SAR ADC Using Wide Range Operation Asynchronous Controller Yosuke Toyama, Akira Shikata, Kentaro Yoshioka, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro (Keio Univ.) SDM2013-80 ICD2013-62 |
This paper presents a wide range in supply voltage, resolution, and sampling rate asynchronous successive approximation ... [more] |
SDM2013-80 ICD2013-62 pp.77-82 |
SDM, ICD |
2013-08-02 13:25 |
Ishikawa |
Kanazawa University |
A Full Asynchronous Nano-Watt SAR ADC by Boosted Power Gaitng Ryo Saito, Ryota Sekimoto, Akira Shikata (Keio Univ) SDM2013-81 ICD2013-63 |
[more] |
SDM2013-81 ICD2013-63 pp.83-87 |
SDM, ICD |
2013-08-02 13:50 |
Ishikawa |
Kanazawa University |
Improvement Linearity of the DAC with Unification of the MOSFET's Operating Region Takumu Yomogita, Cong-Kha Pham (UEC) SDM2013-82 ICD2013-64 |
This paper proposes a linearity improvement method of the Digital-to-Analog Converter (DAC) circuit that can operate in ... [more] |
SDM2013-82 ICD2013-64 pp.89-94 |
SDM, ICD |
2013-08-02 14:25 |
Ishikawa |
Kanazawa University |
[Invited Talk]
A 10th Generation 16-Core SPARC64 Processor for Mission-Critical UNIX Server Ryuji Kan, Tomohiro Tanaka, Go Sugizaki, Ryuichi Nishiyama, Sota Sakabayashi (Fujitsu), Yoichi Koyanagi (Fujitsu Laboratories), Ryuji Iwatsuki, Kazumi Hayasaka (Fujitsu), Taiki Uemura (Fujitsu Semiconductor), Gaku Itou, Yoshitomo Ozeki, Hiroyuki Adachi, Kazuhiro Furuya, Tsuyoshi Motokurumada (Fujitsu) SDM2013-83 ICD2013-65 |
A 10th generation SPARC64 processor is fabricated in enhanced 28nm CMOS process. It runs at 3.0GHz and contains 16 cores... [more] |
SDM2013-83 ICD2013-65 pp.95-98 |
SDM, ICD |
2013-08-02 15:10 |
Ishikawa |
Kanazawa University |
[Invited Talk]
A single chip LTE capable communication processor R-Mobile U2 and its technologies in power management
-- Clock control method by the power saver -- Masaki Fujigaya, Noriaki Sakamoto, Takao Koike, Takahiro Irita, Kohei Wakahara, Tsugio Matsuyama, Keiji Hasegawa, Toshiharu Saito, Akira Fukuda, Kaname Teranishi (Renesas Mobile Corp.), Kazuki Fukuoka, Noriaki Maeda, Koji Nii (Renesas Electronics Corp.), Takeshi Kataoka, Toshihiro Hattori (Renesas Mobile Corp.) SDM2013-84 ICD2013-66 |
The “R-Mobile U2” is a single chip integration of LTE capable base band and 1.5 GHz dual-core application processor. In ... [more] |
SDM2013-84 ICD2013-66 pp.99-103 |