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Technical Committee on VLSI Design Technologies (VLD) (Searched in: 2009)
Search Results: Keywords 'from:2009-09-24 to:2009-09-24'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD | 2009-09-24 13:30 |
Osaka | Osaka University | Fast Global Floorplanning Method Based on Stable-LSE Yasuhiro Takashima, Masatomo Kuwano (Univ. of Kitakyushu)  VLD2009-29 |
[more] | VLD2009-29 pp.1-6 |
| VLD | 2009-09-24 13:55 |
Osaka | Osaka University | A Detail Via Arrangement Method for Reduction of Wire Congestion in 2-Layer Ball Grid Array Packages Masaki Kinoshita, Yoichi Tomioka (Tokyo Inst. of Tech.), Atsushi Takahashi (Osaka Univ.) VLD2009-30 |
A BGA package realizes a lot of connections between a chip and a printed board. The quality of routing design obtained ... [more] |
VLD2009-30 pp.7-12 |
| VLD | 2009-09-24 14:20 |
Osaka | Osaka University | A Wall Generation for Trunk Routing of Multiple Nets on Single Layer Yukihide Kohira (Univ. of Aizu.), Atsushi Takahashi (Osaka Univ.) VLD2009-31 |
In this paper, we propose a wall generation for trunk routing of multiple nets on single layer. An existing routing meth... [more] | VLD2009-31 pp.13-18 |
| VLD | 2009-09-24 15:00 |
Osaka | Osaka University | Complete ILP-Formulation of High-Level Synthesis Keisuke Inoue, Mineo Kaneko (JAIST) VLD2009-32 |
In VLSI design, automatic transformation from an algorithm level behavioral description to a RTL (Register Transfer Leve... [more] | VLD2009-32 pp.19-24 |
| VLD | 2009-09-24 15:25 |
Osaka | Osaka University | A System LSI Design and Verification Environment Using JACKAL Language Takafumi Kohara (Kinki Univ.), Ryuichi Nakawaki (FUJITSU FSAS), Yasuhiro Nagata (NEC System Techno.), Takashi Kambe (Kinki Univ.) VLD2009-33 |
We have been developing an object oriented design system based on “Jackal” language. This System enables us to design an... [more] | VLD2009-33 pp.25-30 |
| VLD | 2009-09-24 15:50 |
Osaka | Osaka University | On accelleration of SER analysis for sequential circuits using implicit enumeration Yusuke Matsunaga, Yusuke Akamine (Kyushu Univ.) VLD2009-34 |
[more] | VLD2009-34 pp.31-36 |
| VLD | 2009-09-24 16:30 |
Osaka | Osaka University | [Invited Talk]
Trace-Driven Workload Simulation Method for Multiprocessor System-On-Chips Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda (Tokyo Inst. of Tech.), Toshiro Isomura, Kazuo Satou (TOYOTA MOTOR CORP.) VLD2009-35 |
[more] | VLD2009-35 p.37 |
| VLD | 2009-09-25 10:00 |
Osaka | Osaka University | An Approach for Algorithm Tuning of Power Grid Simulation by GPGPU Makoto Yokota, Yuuya Isoda, Hisako Sugano, Ittetsu Taniguchi, Masahiro Fukui (Ritsumeikan Univ.) VLD2009-36 |
This paper proposes a speeding up technique for massively parallel power gird simulator by GPGPU (General Purpose comput... [more] | VLD2009-36 pp.39-44 |
| VLD | 2009-09-25 10:25 |
Osaka | Osaka University | Triage Device Slightly Injured Person in Disaster Medical Assistant Network Keishi Sakanushi, Akihito Hiromori (Osaka Univ/JST), Taichiro Imamura, Junya Okamoto (Osaka Univ), Takuji Hieda, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ/JST), Junji Kitamichi (Osaka Univ), Teruo Higashino (Osaka Univ/JST) VLD2009-37 |
[more] | VLD2009-37 pp.45-50 |
| VLD | 2009-09-25 11:05 |
Osaka | Osaka University | High Throughput Irregular LDPC Decoder Based on High-Efficiency Column Operation Unit for IEEE 802.11n Standard Akiyuki Nagashima, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2009-38 |
Low Density Parity Check (LDPC) code is expected to be an error orrecting code for next generation networks since it sho... [more] | VLD2009-38 pp.51-56 |
| VLD | 2009-09-25 11:30 |
Osaka | Osaka University | DFG Mapping for Flexible Engine/Generic ALU Array and Its Dedicated Synthesis Algorithm Ryo Tamura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Makoto Satoh (Hitachi Ltd.) VLD2009-39 |
Reconfigurable processors are those whose contexts are dynamically reconfigured while they are working. We focus on a r... [more] | VLD2009-39 pp.57-62 |
| VLD | 2009-09-25 13:20 |
Osaka | Osaka University | A remote optically reconfigurable gate array using fibers Yumiko Ueno, Minoru Watanabe (Shizuoka Univ.) VLD2009-40 |
[more] | VLD2009-40 pp.63-66 |
| VLD | 2009-09-25 13:45 |
Osaka | Osaka University | A configuration speed acceleration method using negative logic implementation Retsu Moriwaki, Minoru Watanabe (Shizuoka Univ.) VLD2009-41 |
[more] | VLD2009-41 pp.67-70 |
| VLD | 2009-09-25 14:10 |
Osaka | Osaka University | Defect tolerance of a MEMS dynamic optically reconfigurable gate array Daisaku Seto, Minoru Watanabe (Shizuoka Univ.) VLD2009-42 |
[more] | VLD2009-42 pp.71-76 |
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