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Technical Committee on VLSI Design Technologies (VLD) (Searched in: 2008)
Search Results: Keywords 'from:2009-03-11 to:2009-03-11'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD | 2009-03-12 13:25 |
Okinawa | A Proposal of an Adaptive Network on Chip for Multi-Core SoC Hiroshi Kadota (Kyushu Univ.), Akiyoshi Wakatani (Konan Univ)  VLD2008-146 |
The Network-on-Chip (NoC) for today’s multi/many-core architecture should be evaluated by its power dissipation rather t... [more] | VLD2008-146 pp.117-122 |
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| VLD | 2009-03-12 13:50 |
Okinawa | A hardmacro placement approach to reduce communication energy for deterministic-routing-based NoC Hiroshi Uchikoshi (Toyohashi Univ. of Tech.), Makoto Sugihara (Toyohashi Univ. of Tech./JST-CREST) VLD2008-147 |
An on-chip bus architecture is utilized as a communication architecture of a System-on-a-Chip. It is difficult to incre... [more] |
VLD2008-147 pp.123-128 |
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| VLD | 2009-03-12 14:15 |
Okinawa | Automatic generation of Network-on-Chip topology under link length and latency constraint Hideo Tanida (Univ. of Tokyo), Hiroaki Yoshida (Univ. of Tokyo/JST-CREST), Takeshi Matsumoto (Univ. of Tokyo), Masahiro Fujita (Univ. of Tokyo/JST-CREST) VLD2008-148 |
With wire delay becoming dominant compared to transistor delay in deep-submicron era, the performance of SoC is more aff... [more] | VLD2008-148 pp.129-134 |
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| VLD | 2009-03-12 14:50 |
Okinawa | A ring segmented bus architrcture for Globally Asynchronous Locally Synchronous System Masafumi Kondo, Yoichiro Sato (Okayama Prefectural Univ), Kazuyuki Tashiro (FUJITSU TEN), Tomoyuki Yokogawa, Michiyoshi Hayase (Okayama Prefectural Univ) VLD2008-149 |
Recently, most digital systems are designed as GALS (Globally Asynchronous Locally Synchronous) systems. Several archit... [more] |
VLD2008-149 pp.135-140 |
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| VLD | 2009-03-12 15:15 |
Okinawa | Formal verification of GALS system designs using UPPAAL Kazuaki Kirita, Tomoyuki Yokogawa, Hisashi Miyazaki, Yoichiro Sato, Michiyoshi Hayase (Okayama Pref. Univ.) VLD2008-150 |
To design GALS (Globally Asynchronous Locally Synchronous) systems, it is necessary to verify the correctness of behavi... [more] |
VLD2008-150 pp.141-146 |
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| VLD | 2009-03-12 15:40 |
Okinawa | A Task Mapping Algorithm for Task Chaining Network Processor by Backtracking Keita Saito, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2008-151 |
To meet increasing demands of link speeds and complex network applications, network processor is required because it has... [more] | VLD2008-151 pp.147-152 |
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| VLD | 2009-03-12 16:05 |
Okinawa | Delay Reduction Algorithm by Balancing Distribution of Traffic for Odd-Even Turn Model in NoCs Shingo Wakita, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2008-152 |
It is necessary to suppress the average delay to low when the packet is forwarded from a source node to the destination ... [more] | VLD2008-152 pp.153-158 |
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| VLD | 2009-03-12 16:40 |
Okinawa | Low Power Deblocking Filter Implementation Method for H.264/AVC Yoshinori Hayashi, Tomohiro Akita, Tian Song, Takashi Shimamoto (Tokushima Univ.) VLD2008-153 |
This paper presents a low power architecture for deblocking filter of the H.264/AVC. Deblocking filtering accounts for f... [more] | VLD2008-153 pp.159-164 |
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| VLD | 2009-03-12 17:05 |
Okinawa | Transform and Quantization Architecture with All-Zero Detection and Bit Estimation for H.264/AVC Hiroki Kuniyasu, Tomoyuki Kishida, Tian Song, Takashi Shimamoto (Tokushima Univ.) VLD2008-154 |
H.264/AVC introduced a certain numbers of novel prediction modes compared to the previous standards. Rate-Distortion Opt... [more] | VLD2008-154 pp.165-170 |
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| VLD | 2009-03-12 17:30 |
Okinawa | Asynchronous $\pm2^k$ Gray-Code Adder Shinya Matsuyama, Takashi Hisakado (Kyoto Univ.) VLD2008-155 |
The topological property of Gray code, that only one bit of the code is changed when its representing integer is one inc... [more] | VLD2008-155 pp.171-176 |
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| VLD | 2009-03-13 09:15 |
Okinawa | An algorithm for building RTL library Masato Kawai, Hirofumi Kawauchi, Toshio Morikawa, Masaaki Ohtsuki, Masahiro Fukui (Ritsumeikan Univ.) VLD2008-156 |
Recently, due to the appearance of high-performance mobile electrical appliances and rapid growth of the electrical syst... [more] | VLD2008-156 pp.177-182 |
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| VLD | 2009-03-13 09:40 |
Okinawa | A Battery Charge/Discharge Simulator Close to Actual Behavior Sayaka Iwakoshi, Keita Kojima, Kazunori Toi, Masahiro Fukui (Ritsumeikan Univ.) VLD2008-157 |
Accompanying with the rapid popularization of portable equipments in recent years, the battery technology continues a re... [more] | VLD2008-157 pp.183-188 |
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| VLD | 2009-03-13 10:05 |
Okinawa | A Study for Power Grid Simulator by using GPU Hisako Sugano, Shinichi Nishizawa, Taiki Hashizume, Masahiro Fukui (Ritsumeikan Univ.) VLD2008-158 |
The rapidity of technical innovation of GPU is much faster than CPU and above Moore’s law. Recently, there are some exam... [more] | VLD2008-158 pp.189-194 |
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| VLD | 2009-03-13 10:40 |
Okinawa | Layout Aware Cell Clustering for Body Biasing Koichi Hamamoto (Osaka Univ.), Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye (Osaka Univ./JST-CREST) VLD2008-159 |
Body bias control has been widely studied for performance compensation. In order to reduce leakage increase involved by ... [more] | VLD2008-159 pp.195-200 |
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| VLD | 2009-03-13 11:05 |
Okinawa | Correlation Verification between Transistor Variability Model with Body Biasing and Ring Oscillation Frequency in Subthreshold Circuits Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye (Osaka Univ./JST-CREST) VLD2008-160 |
This paper presents modeling of manufacturing variability and body bias effect for subthreshold circuits based on mea... [more] |
VLD2008-160 pp.201-206 |
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| VLD | 2009-03-13 11:30 |
Okinawa | Decoupling Capacitance Allocation for Timing with Statistical Noise Model and Timing Analysis Takashi Enami, Masanori Hashimoto (Osaka Univ.), Takashi Sato (Tokyo Inst. of Tech.) VLD2008-161 |
This paper presents an allocation method of decoupling capacitance that explicitly considers timing. We have found and ... [more] |
VLD2008-161 pp.207-212 |
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| VLD | 2009-03-13 13:00 |
Okinawa | Implementation and performance measurement of low-power multiplier applying Run Time Power Gating Mitsutaka Nakata, Toshiaki Shirai (Shibaura Inst. of Tech.), Seidai Takeda (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. of Tech.) VLD2008-162 |
This paper describes an implementation of low power multiplier applying Run Time Power Gating using 90nm process. Leakag... [more] | VLD2008-162 pp.213-218 |
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| VLD | 2009-03-13 13:25 |
Okinawa | Physical design and Evaluation of On-chip Leakage Monitor at 65nm devices Satoshi Koyama, Kimiyoshi Usami (Shibaura Inst. of Tech.) VLD2008-163 |
[more] | VLD2008-163 pp.219-224 |
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| VLD | 2009-03-13 13:50 |
Okinawa | Performance Evaluations of nMOS Level Shifter Circuits Makoto Otsu, Shuji Tsukiyama (Chuo Univ.), Isao Shirakawa (Univ. of Hyogo), Shuji Nishi, Tomoyuki Nagai, Yasushi Kubota (Sharp Corp.) VLD2008-164 |
Driver circuits for small liquid crystal displays are usually formed on the same glass as the liquid crystal. Hence, if... [more] | VLD2008-164 pp.225-230 |
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| VLD | 2009-03-13 14:15 |
Okinawa | Performance Evaluations of Two Measures for Statistical Design Yuki Yoshida, Shingo Takahashi, Shuji Tsukiyama (Chuo Univ.) VLD2008-165 |
In order to establish statistical design methodologies for LSI design, not only the statistical static timing analysis b... [more] | VLD2008-165 pp.231-236 |
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