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Technical Committee on VLSI Design Technologies (VLD)  (Searched in: 2008)

Search Results: Keywords 'from:2009-01-29 to:2009-01-29'
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Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Ascending)
 Results 21 - 35 of 35 [Previous]  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, CPSY, RECONF, IPSJ-SLDM 2009-01-30
09:40		 Kanagawa   Foreknown Regularity Arithmetic Processing Unit
Jin Sato, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.) VLD2008-111 CPSY2008-73 RECONF2008-75		 The paper proposes a method of designing an arithmetic unit based on the regularity of the output depending on input pat... [more] VLD2008-111 CPSY2008-73 RECONF2008-75
pp.117-122
VLD, CPSY, RECONF, IPSJ-SLDM 2009-01-30
10:05		 Kanagawa   Improvement of Search Efficiency by Principal Component Analysis for Analog Circuit Sizing of Operational Amplifier using Genetic Algorithm
Yuji Takehara (Toyohashi Univ. Tech.), Masanori Natsui (Tohoku Univ.), Yoshiaki Tadokoro (Toyohashi Univ. Tech.) VLD2008-112 CPSY2008-74 RECONF2008-76		 This paper presents an automatic sizing of analog circuits using genetic algorithm (GA) and its performance improvement ... [more] VLD2008-112 CPSY2008-74 RECONF2008-76
pp.123-128
VLD, CPSY, RECONF, IPSJ-SLDM 2009-01-30
10:30		 Kanagawa   A study for accurate RTL timing modeling
Shota Nakajima, Masahiro Fukui (Ritsumeikan Univ.) 		Recent, due to the rapid progress of LSI technology, efficient and low-power designs have been highly required to keep h... [more] VLD2008-113 CPSY2008-75 RECONF2008-77
pp.129-134
VLD, CPSY, RECONF, IPSJ-SLDM 2009-01-30
10:55		 Kanagawa   Interaction of Abstraction Processing for Creation of Ideas -- An Electronic Brain like a thought of human being --
Tadayuki Hattori VLD2008-114 CPSY2008-76 RECONF2008-78		 How to construct an artificial electronic brain like a thought of a human being? I show fundamental architecture of the ... [more] VLD2008-114 CPSY2008-76 RECONF2008-78
pp.135-140
VLD, CPSY, RECONF, IPSJ-SLDM 2009-01-30
12:20		 Kanagawa   A Multi-layer Bus Architecture Optimization Algorithm for MPSoC in Embedded Systems
Harunobu Yoshida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Masayoshi Tachibana (KUT) VLD2008-115 CPSY2008-77 RECONF2008-79		 In this paper, we propose an on-chip bus optimization algorithm for a multi-layer bus architecture. Our algorithm effici... [more] VLD2008-115 CPSY2008-77 RECONF2008-79
pp.141-146
VLD, CPSY, RECONF, IPSJ-SLDM 2009-01-30
12:45		 Kanagawa   A Low Energy ASIP Synthesis Method Based on Reducing Instruction Memory Access
Yuta Kobayashi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2008-116 CPSY2008-78 RECONF2008-80		 In this paper, we propose an energy-efficient ASIP synthesis method based on reducing instruction memory access. Since a... [more] VLD2008-116 CPSY2008-78 RECONF2008-80
pp.147-152
VLD, CPSY, RECONF, IPSJ-SLDM 2009-01-30
13:10		 Kanagawa   Combine operation pattern extraction from CDFG for DSP generation
Toshiyuki Kato, Takaaki Miyake, Shinichi Oomata, Hideto Nishikado, Hironori Yamauchi (Ritsumei Univ), Shiro Kobayashi (Asahi Kasei) VLD2008-117 CPSY2008-79 RECONF2008-81		 In this paper, we propose a method to extract frequent operation patterns from the CDFG used to Mostright Expantion and ... [more] VLD2008-117 CPSY2008-79 RECONF2008-81
pp.153-158
VLD, CPSY, RECONF, IPSJ-SLDM 2009-01-30
13:45		 Kanagawa   Customizing of Domain-Specific and Compact Reconfigurable HW
Shogo Nakaya, Nobuki Kajihara, Toru Awashima (NEC) VLD2008-118 CPSY2008-80 RECONF2008-82		 Domain-specific reconfigurable HWs, which have limited flexibility depending on applications, are expected as small prog... [more] VLD2008-118 CPSY2008-80 RECONF2008-82
pp.159-164
VLD, CPSY, RECONF, IPSJ-SLDM 2009-01-30
14:10		 Kanagawa   Delay Evaluation of 90nm CMOS Multi-Context FPGA for Large-Scale Circuit Emulation
Naoto Miyamoto, Tadahiro Ohmi (Tohoku Univ.) VLD2008-119 CPSY2008-81 RECONF2008-83		 For large-scale circuit emulation with using a multi-context FPGA (MC-FPGA), a circuit is divided into multiple sub-circ... [more] VLD2008-119 CPSY2008-81 RECONF2008-83
pp.165-170
VLD, CPSY, RECONF, IPSJ-SLDM 2009-01-30
14:45		 Kanagawa   Implementation of Asynchronous Bus for GALS System
Takehiro Hori, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.) VLD2008-120 CPSY2008-82 RECONF2008-84		 Although asynchronous circuit can solve problems of power consumption, speed, noise, and clockskew, the transmission is ... [more] VLD2008-120 CPSY2008-82 RECONF2008-84
pp.171-176
VLD, CPSY, RECONF, IPSJ-SLDM 2009-01-30
15:10		 Kanagawa   A Study of Routing Architecture on Variable Grain Logic Cell for DSP Application
Yoshiaki Satou, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) VLD2008-121 CPSY2008-83 RECONF2008-85		 A Reconfigurable Logic Device (RLD), which has circuit programmability, is applied to embedded systems as a hardware Int... [more] VLD2008-121 CPSY2008-83 RECONF2008-85
pp.177-182
VLD, CPSY, RECONF, IPSJ-SLDM 2009-01-30
15:35		 Kanagawa   Research on an Interconnection Network of the Dynamically Reconfigurable Processor: MuCCRA
Masaru Kato, Toru Sano, Hideharu Amano (Keio Univ) VLD2008-122 CPSY2008-84 RECONF2008-86		 In the MuCCRA(Multi-Core Configurable Reconfigurable Architecture)
project, an architecture of configurable low-power m... [more]		 VLD2008-122 CPSY2008-84 RECONF2008-86
pp.183-188
VLD, CPSY, RECONF, IPSJ-SLDM 2009-01-30
16:10		 Kanagawa   An Architecture of Regular Expression Matching Machine for NIDS and Its FPGA Implementation
Yosuke Kawanaka, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ) VLD2008-123 CPSY2008-85 RECONF2008-87		 This paper proposes an organization of special-purpose hardware dedicated to pattern matching for packet inspection in n... [more] VLD2008-123 CPSY2008-85 RECONF2008-87
pp.189-194
VLD, CPSY, RECONF, IPSJ-SLDM 2009-01-30
16:35		 Kanagawa   An FPGA implementation of Gibbs sampling method towards high-speed motif search
Yuka Sato, Junko Tazawa, Toshiaki Miyazaki (Univ. of Aizu) VLD2008-124 CPSY2008-86 RECONF2008-88		 It is very important to detect a common motif, i.e., partial base sequence, from DNA sequences in bioinformatics researc... [more] VLD2008-124 CPSY2008-86 RECONF2008-88
pp.195-199
VLD, CPSY, RECONF, IPSJ-SLDM 2009-01-30
17:00		 Kanagawa   Fast Solution of Link Disjoint Path Algorithm on Parallel Reconfigurable Processor DAPDNA-2
Taku Kihara, Sho Shimizu, Shan Gao, Yutaka Arakawa, Naoaki Yamanaka (Keio Univ.), Akifumi Watanabe (IPFlex) VLD2008-125 CPSY2008-87 RECONF2008-89		 In next generation network, a high level reliabilty is strong required. In a protection, which is the one of network sur... [more] VLD2008-125 CPSY2008-87 RECONF2008-89
pp.201-206
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