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Technical Committee on VLSI Design Technologies (VLD) (Searched in: 2008)
Search Results: Keywords 'from:2009-01-29 to:2009-01-29'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-29 08:40 |
Kanagawa | Implementation of Dynamically Reconfigurable Processor MuCCRA-3 and Methods for Reconfiguration Overhead Reduction Toru Sano, Hideharu Amano (Keio Univ)  VLD2008-91 CPSY2008-53 RECONF2008-55 |
We have developed and evaluated MuCCRA-1 and 2 in order to analyze architectural trade-off in dynamically reconfigurab... [more] |
VLD2008-91 CPSY2008-53 RECONF2008-55 pp.1-6 |
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| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-29 09:05 |
Kanagawa | Evaluation of a Multicore Reconfigurable Architecture Vu Manh Tuan, Hiroki Matsutani, Naohiro Katsura, Hideharu Amano (Keio Univ.) VLD2008-92 CPSY2008-54 RECONF2008-56 |
A multicore reconfigurable architecture consisting of multiple small computational cores connected by an interconnection... [more] | VLD2008-92 CPSY2008-54 RECONF2008-56 pp.7-12 |
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| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-29 09:30 |
Kanagawa | Power Reduction of Dynamically Reconfigurable Processor using Dual-Vth Technologies Keiichiro Hirai, Toru Sano, Masaru Kato, Hideharu Amano (Keio Univ.) VLD2008-93 CPSY2008-55 RECONF2008-57 |
[more] | VLD2008-93 CPSY2008-55 RECONF2008-57 pp.13-17 |
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| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-29 10:05 |
Kanagawa | Implementation and evaluation of arithmetic circuit for Poisson equation that aims at TFlops by using FPGA array Kazuki Sato, Baatarsuren Bars, Masatoshi Sekine (Tokyo Univ. of Agriculture and Tech.) VLD2008-94 CPSY2008-56 RECONF2008-58 |
In recent years, the examples which use FPGA for the HPC use are increasing. We propose FPGA array which accumulated a l... [more] | VLD2008-94 CPSY2008-56 RECONF2008-58 pp.19-24 |
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| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-29 10:30 |
Kanagawa | FPGA Implementation of Metastability-based True Random Number Generator Hisashi Hata, Shuichi Ichikawa (TUT) VLD2008-95 CPSY2008-57 RECONF2008-59 |
Metastability of RS latch is utilizable as an entropy source for true random number generators (TRNG). This kind of TRNG... [more] | VLD2008-95 CPSY2008-57 RECONF2008-59 pp.25-30 |
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| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-29 10:55 |
Kanagawa | A Proposal of Message Driven IP Core Interface Ryuta Sasaki, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.) VLD2008-96 CPSY2008-58 RECONF2008-60 |
In a ULSI such as SoC, various IP cores with different development firms are integrated in single-chip. Therefore proble... [more] | VLD2008-96 CPSY2008-58 RECONF2008-60 pp.31-36 |
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| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-29 12:20 |
Kanagawa | A programmable 9-contexts optically reconfigurable gate arrays and its writer Shinya Kubota, Minoru Watanabe (Shizuoka Univ.) VLD2008-97 CPSY2008-59 RECONF2008-61 |
[more] | VLD2008-97 CPSY2008-59 RECONF2008-61 pp.37-40 |
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| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-29 12:45 |
Kanagawa | Perfect demonstration of a four-context Optically Reconfigurable Gate Array Takayuki Mabuchi, Minoru Watanabe (Shizuoka Univ.) VLD2008-98 CPSY2008-60 RECONF2008-62 |
[more] | VLD2008-98 CPSY2008-60 RECONF2008-62 pp.41-44 |
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| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-29 13:10 |
Kanagawa | Comparison evaluation of an inversion/non-inversion dynamic optically reconfiguration architecture Shinichi Kato, Minoru Watanabe (Shizuoka Univ.) VLD2008-99 CPSY2008-61 RECONF2008-63 |
[more] | VLD2008-99 CPSY2008-61 RECONF2008-63 pp.45-50 |
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| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-29 13:45 |
Kanagawa | Circuit Partition Method with Time-multiplexed I/O Tatsuki Isomura (Univ. of Kitakyushu), Masato Inagi (Hiroshima City Univ.), Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC) VLD2008-100 CPSY2008-62 RECONF2008-64 |
We propose a partition method to prototype a large scaled system with time-multiplexed I/Os. Recent prototyping of a lar... [more] | VLD2008-100 CPSY2008-62 RECONF2008-64 pp.51-55 |
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| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-29 14:10 |
Kanagawa | An Efficient Cut Enumeration for Depth-Optimum Technology Mapping for LUT-based FPGAs Taiga Takata, Yusuke Matsunaga (Kyushu Univ.) |
This paper presents a top-down cut enumeration for depth-minimum technology mapping for LUT-based FPGAs. Enumerating all... [more] | VLD2008-101 CPSY2008-63 RECONF2008-65 pp.57-62 |
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| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-29 14:45 |
Kanagawa | A Proposal of the Computer Architecture for Numbers of Arbitrary Word Length Shohei Hashimoto, Yuta Totsuka, Masamichi Makino, Hikaru Yasuda, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara (Tokyo Denki Univ.) VLD2008-102 CPSY2008-64 RECONF2008-66 |
We propose a computer architecture for numbers of arbitrary word length with unlimited processing data length. In this d... [more] | VLD2008-102 CPSY2008-64 RECONF2008-66 pp.63-68 |
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| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-29 15:10 |
Kanagawa | Improvement of Execution Efficiency by Applying Unitable PE Architecture for MX Core Yuta Mizokami, Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) VLD2008-103 CPSY2008-65 RECONF2008-67 |
MX-Core is a massively parallel SIMD(Single Instruction Multiple Data) type processor which have ne-grained computing u... [more] | VLD2008-103 CPSY2008-65 RECONF2008-67 pp.69-74 |
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| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-29 15:35 |
Kanagawa | An Experimental Linux Cluster System for Tests Koichi Kitano (Polytech.Univ.), Koji Teramoto (EHDO), Tadayoshi Horita (Polytech.Univ.) VLD2008-104 CPSY2008-66 RECONF2008-68 |
Most computer cluster, which is produced by a company, is so expensive compared to a PC, and the versions of its operati... [more] | VLD2008-104 CPSY2008-66 RECONF2008-68 pp.75-79 |
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| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-29 16:10 |
Kanagawa | Extension of High Level Synthesis system CCAP for AMP multi-core system desin Yoshiyuki Ishimori, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Nagoya Univ.), Hiroyuki Kanbara (ASTEM) VLD2008-105 CPSY2008-67 RECONF2008-69 |
[more] | VLD2008-105 CPSY2008-67 RECONF2008-69 pp.81-86 |
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| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-29 16:35 |
Kanagawa | A Tunable LSI Based on Timing Skew and Stall Adjustments Yayumi Uehara, Mineo Kaneko (JAIST) VLD2008-106 CPSY2008-68 RECONF2008-70 |
With the advance of process technologies, delay variations become relatively larger. As a result, it becomes difficult t... [more] | VLD2008-106 CPSY2008-68 RECONF2008-70 pp.87-92 |
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| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-29 17:00 |
Kanagawa | Fast Module Placement in Floorplan-aware High-level Synthesis Wataru Sato, Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2008-107 CPSY2008-69 RECONF2008-71 |
As device feature size decreases, interconnect delay becomes the dominating factor of total delay. Therefore it is neces... [more] | VLD2008-107 CPSY2008-69 RECONF2008-71 pp.93-98 |
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| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-29 17:25 |
Kanagawa | A Fast SIMD Processing Unit Synthesis Method with Optimal Pipeline Architecture for Application-specific Processors Takayuki Watanabe, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2008-108 CPSY2008-70 RECONF2008-72 |
Small area, high performance and high productivity are required for application-specific processors in embedded systems.... [more] | VLD2008-108 CPSY2008-70 RECONF2008-72 pp.99-104 |
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| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-30 08:40 |
Kanagawa | Automatic Equivalence Specification between Two Sequential Circuits in High-level Design Jinmei Xu, Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita (University of Tokyo) VLD2008-109 CPSY2008-71 RECONF2008-73 |
[more] | VLD2008-109 CPSY2008-71 RECONF2008-73 pp.105-110 |
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| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-30 09:05 |
Kanagawa | Formal Verification Method for Protocol Transducer Using Automatically Generated Properties from Specification Fei Gao, Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita (Univ. of Tokyo) VLD2008-110 CPSY2008-72 RECONF2008-74 |
IP-reuse design is widely applied in order to reduce design period by utilizing already designed and well verified modul... [more] | VLD2008-110 CPSY2008-72 RECONF2008-74 pp.111-116 |
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