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Technical Committee on VLSI Design Technologies (VLD) (Searched in: 2017)
Search Results: Keywords 'from:2018-02-28 to:2018-02-28'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, HWS (Joint) |
2018-03-01 10:55 |
Okinawa | Okinawa Seinen Kaikan | Implementation and Evaluation of MCTS-Based Parallel Prefix Adder Synthesis Taeko Matsunaga (NBU), Yusuke Matsunaga (Kyushu Univ.) |
[more] | |
| VLD, HWS (Joint) |
2018-03-01 11:20 |
Okinawa | Okinawa Seinen Kaikan |  VLD2017-109 |
[more] | VLD2017-109 pp.121-126 |
| VLD, HWS (Joint) |
2018-03-01 13:00 |
Okinawa | Okinawa Seinen Kaikan | An Evaluation of Graph Reduction Technique for Delay Insertion of General-Synchronous Circuit Yuki Arai, Shuji Tsukiyama (Chuo Univ.) VLD2017-110 |
In general-synchronous framework, the clock signal is distributed to each register in optimal individual timing, so that... [more] | VLD2017-110 pp.127-132 |
| VLD, HWS (Joint) |
2018-03-01 13:25 |
Okinawa | Okinawa Seinen Kaikan | A Study on Energy Optimization for Asynchronous RTL Models with Bundled-data Implementation Shogo Semba, Hiroshi Saito (UoA) VLD2017-111 |
In this work, we study two energy optimization methods for asynchronous RTL models with bundled-data implementation. The... [more] | VLD2017-111 pp.133-138 |
| VLD, HWS (Joint) |
2018-03-01 13:50 |
Okinawa | Okinawa Seinen Kaikan | Evaluating logic encryption methods using error correcting logic synthesis Yusuke Matsunaga (Kyushu Univ.) VLD2017-112 |
[more] | VLD2017-112 pp.139-144 |
| VLD, HWS (Joint) |
2018-03-01 14:30 |
Okinawa | Okinawa Seinen Kaikan | A SW/HW Partitioning for Model Based Design
-- A automated SW/HW partitioning using Matlab/Simulink and C based High Level Synthesis -- Ryo Yamamoto, Koki Murano, Ayumu Yamamoto, Yoshihiro Ogawa (Mitsubishi Electric) VLD2017-113 |
[more] | VLD2017-113 pp.145-150 |
| VLD, HWS (Joint) |
2018-03-01 14:55 |
Okinawa | Okinawa Seinen Kaikan | Core allocation with mixed multirate tasks in model-based parallelization Yoshihiro Ikeda, Masato Edahiro (Nagoya Univ) VLD2017-114 |
In recent embedded systems, multi-core processors and parallel programming are introduced to improve performance.Also, l... [more] | VLD2017-114 pp.151-156 |
| VLD, HWS (Joint) |
2018-03-01 15:20 |
Okinawa | Okinawa Seinen Kaikan | Hardware/Software co-design environment in model-based parallelization (MBP) Kazuki Kashiwabara, Shinya Honda, Masato Edahiro (Nagoya Univ.) VLD2017-115 |
In recent years, while the complexity and high performance of in-vehicle systems are progressing, restrictions on time a... [more] | VLD2017-115 pp.157-162 |
| VLD, HWS (Joint) |
2018-03-01 16:00 |
Okinawa | Okinawa Seinen Kaikan | A C Description Approach for High Level Synthesis to Configure DNN Inference Circuit Takuya Okamoto, Ryota Yamamoto, Shinya Honda (Nagoya Univ.) VLD2017-116 |
Today, Deep Neural Network (DNN) is utilized in various fields. There is a demand for deep learning in the field of embedd... [more] | VLD2017-116 pp.163-168 |
| VLD, HWS (Joint) |
2018-03-01 16:25 |
Okinawa | Okinawa Seinen Kaikan | A Concept of DNN Framework for Embedded System Using FPGA Ryota Yamamoto, Takuya Okamoto, Shinya Honda (Nagoya Univ.), Qian Zhao, Toki Matsumoto, Yukikazu Nakamoto (Hyogo Univ.), Tamotsu Sakai, Tetsuya Aoyama, Kazutoshi Wakabayashi (NEC) VLD2017-117 |
Recently, a DNN (Deep Neural Network) is used in many areas, and it required a field of an embedded system. For an em... [more] |
VLD2017-117 pp.169-174 |
| VLD, HWS (Joint) |
2018-03-01 16:50 |
Okinawa | Okinawa Seinen Kaikan | Impedance Evaluation Mechanism with Automatic Calibration based on Automatic Balanced Bridge Takaaki Shirakawa, Sakai Ryosuke, Nakatake Shigetoshi (Univ. of Kitakyusyu) VLD2017-118 |
We propose a circuit mechanism with an automatic calibration in the impedance measurement circuit based on the aut... [more] |
VLD2017-118 pp.175-179 |
| VLD, HWS (Joint) |
2018-03-02 09:00 |
Okinawa | Okinawa Seinen Kaikan | On-chip and ultra low current measurement circuit based on potentiostat method Daishi Isogai, Takaaki Shirakawa, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2017-119 |
We propose a current measurement circuit using on - chip high resistance by MOSFET. Due to advances in biosensing techno... [more] | VLD2017-119 pp.181-186 |
| VLD, HWS (Joint) |
2018-03-02 09:25 |
Okinawa | Okinawa Seinen Kaikan | A study on interconnect delay computation for via-switch based FPGA Yuki Nakazawa, Ryutaro Doi, Jaehoon Yu, Masanori Hashimoto (Osaka Univ.) VLD2017-120 |
(To be available after the conference date) [more] | VLD2017-120 pp.187-192 |
| VLD, HWS (Joint) |
2018-03-02 09:50 |
Okinawa | Okinawa Seinen Kaikan | Approximate computing based on extension of DRAM refresh interval and data correction Takamasa Fukasawa, Kimiyoshi Usami (SIT) VLD2017-121 |
As DRAM capacity increases, there is concern that energy consumption will increase due to the refresh. Therefore, we pro... [more] | VLD2017-121 pp.193-198 |
| VLD, HWS (Joint) |
2018-03-02 10:30 |
Okinawa | Okinawa Seinen Kaikan | Implementation of Reconfigurable Accelerator Cool Mega-Array Using MTJ-based Nonvolatile Flip-Flop Enabling to Verify Stored Data Junya Akaike, Kimiyoshi Usami, Masaru Kudo (SIT), Hideharu Amano, Takeharu Ikezoe (Keio Univ.), Keizo Hiraga, Yusuke Shuto, Kojiro Yagami (Sony SS) VLD2017-122 |
As a method of reducing the power consumption of the flip-flop circuit, there is a nonvolatile flip-flop (NVFF) that ena... [more] | VLD2017-122 pp.199-204 |
| VLD, HWS (Joint) |
2018-03-02 10:55 |
Okinawa | Okinawa Seinen Kaikan | Experimental study on power reduction by approximate computing with voltage over-scaling Masahiro Sato, Yutaka Masuda, Masanori Hashimoto (Osaka Univ.) VLD2017-123 |
(To be available after the conference date) [more] | VLD2017-123 pp.205-210 |
| VLD, HWS (Joint) |
2018-03-02 11:20 |
Okinawa | Okinawa Seinen Kaikan | Energy Reduction of Standard-Cell Memory Exploiting Selective Activation Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ.) VLD2017-124 |
On-chip memories have a large impact on energy-efficiency of LSI circuits. This paper discusses energy-efficient on-chip... [more] | VLD2017-124 pp.211-216 |
| VLD, HWS (Joint) |
2018-03-02 13:00 |
Okinawa | Okinawa Seinen Kaikan | [Invited Talk]
Cyber attacks and countermeasures for smart factories in the Age of Industry 4.0 Takeshi Yoneda (Mitsubishi Electric Corp.) VLD2017-125 |
In the age of Industry 4.0, smart factories are connected through internet. So they need countermeasures against sophist... [more] | VLD2017-125 pp.217-224 |
| VLD, HWS (Joint) |
2018-03-02 14:05 |
Okinawa | Okinawa Seinen Kaikan | PL-PUF Implementation by Improvement of Capturing Timing Control Circuit Yasuhiro Ogasahara, Yohei Hori, Hanpei Koike (AIST) VLD2017-126 |
In this study, we demonstrate the first implementation of a pseudo linear feedback shift register physical unclonable fu... [more] | VLD2017-126 pp.225-229 |
| VLD, HWS (Joint) |
2018-03-02 14:30 |
Okinawa | Okinawa Seinen Kaikan | Modeling Attacks on Double-Arbiter PUF Using Deep Neural Network Tomoki Iizuka, Hiromitsu Awano, Makoto Ikeda (UTokyo) VLD2017-127 |
A deep neural network-based modeling attack for Double-Arbiter PUF (DAPUF) is proposed. Although DAPUF is known to be hi... [more] | VLD2017-127 pp.231-236 |
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