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Technical Committee on VLSI Design Technologies (VLD) (Searched in: 2015)
Search Results: Keywords 'from:2015-12-01 to:2015-12-01'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 11:40 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | A Software-Oriented Design and Synthesis Platform for a Construction of Real-Time Systems on Programmable SoCs Takuya Hatayama, Yusuke Tani, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.)  RECONF2015-53 |
We have been developing SWORDS platform, a SoftWare ORiented Design and Synthesis platform.SWORDS platform aims at impro... [more] | RECONF2015-53 pp.27-32 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 12:05 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | A Study on DVFS for Heterogeneous Task Set Mineo Kaneko (JAIST) VLD2015-47 DC2015-43 |
[more] | VLD2015-47 DC2015-43 pp.63-68 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 11:15 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | A C Framework for Integrating Algorithm Description and CGRA Implementation Yasuhiko Nakashima (NAIST) CPSY2015-65 |
We need high-speed, low-cost and low-power embedded computers for intelligent IoT devices. In contrast to vector acceler... [more] | CPSY2015-65 pp.21-26 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 11:40 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Performance Comparison of FPGA Accelerators with Vivado HLS and PyCoRAM Yuma Kikutani (OPUCT), Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) CPSY2015-66 |
High-level synthesis (HLS) technology has been an attractive and efficient method for FPGA system development. In this ... [more] | CPSY2015-66 pp.27-32 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 12:05 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | A proposal of the light field image compression and decompression using HEVC Takamasa Mitani, Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) CPSY2015-67 |
A light field image is a type of images that can refocus and extend the depth of field by post processing. A light field... [more] | CPSY2015-67 pp.33-38 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 13:45 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | [Invited Talk]
Towards Getting Your Paper Accepted at International Conferences
-- Based on Experiences of Studying Abroad and Serving as a Program Committee Member -- Yuko Hara-Azumi (Tokyo Tech) VLD2015-48 DC2015-44 |
[more] | VLD2015-48 DC2015-44 p.69 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 14:25 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | [Invited Talk]
Taipei Report Yasuhiro Takashima (Univ. of Kitakyushu) VLD2015-49 DC2015-45 |
[more] | VLD2015-49 DC2015-45 p.71 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 14:55 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | [Invited Talk]
EDA Research Activities in The University of Texas at Austin Tetsuaki Matsunawa (Toshiba) VLD2015-50 DC2015-46 |
International competition in EDA research is getting more intense. In major international conference, such as DAC or IC... [more] |
VLD2015-50 DC2015-46 p.73 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 13:45 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | A Preliminary Evaluation of Linear Network Using ThruChip Interface Akio Nomura, Hiroki Matsutani, Yasuhiro Take (Keio Univ.), Mitaro Namiki (Tokyo Univ. of Agriculture and Technology), Tadahiro Kuroda, Hideharu Amano (Keio Univ.) CPSY2015-68 |
(To be available after the conference date) [more] | CPSY2015-68 pp.39-44 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 14:10 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | CSMA/CD and D-TDMA Hybrid Wireless 3D Bus Architecture Go Matsumura (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano, Hiroki Matsutani (Keio Univ.) CPSY2015-69 |
(To be available after the conference date) [more] | CPSY2015-69 pp.45-50 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 14:35 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Performance Evaluation of K-best Viterbi Decoder for IoT Applications Thi Hong Tran (NAIST), Dwi Rahma Ariyani, Lina Alfaridah ZH (Andalas Univ.), Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima (NAIST) CPSY2015-70 |
[more] | CPSY2015-70 pp.51-56 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 15:00 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Problems that occur in FPGAs communication
-- Cautionary point of PCIe Gen3 -- Hirotaka Takayama, Yoshiki Yamaguchi (Tsukuba Univ.) RECONF2015-54 |
The purpose of this study investigates of suppressed bandwidth problem of PCI-Express. This problem makes communication ... [more] | RECONF2015-54 pp.33-38 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 13:45 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Design of low power AFE circuit supporting IR array sensor for human detection Shota Ueguchi (Ritsumeikan Univ.), Toshio Kumamoto (Osaka Sangyo Univ.), Masayoshi Shirahata, Takeshi Kumaki, Takeshi Fujino (Ritsumeikan Univ.) CPM2015-129 ICD2015-54 |
We are developing the technology of human monitoring camera systems using intermittent-sensing scheme. In this system, t... [more] | CPM2015-129 ICD2015-54 pp.11-16 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 14:10 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | A Design of a Quick-Lock All-Digital CDR with Improved Jitter Performance by Fractional Phase Selection Technique Norihito Tohge, Tetsuya Iizuka, Toru Nakura (Univ. of Tokyo), Satoshi Miura, Yoshimichi Murakami (THine), Kunihiro Asada (Univ. of Tokyo) CPM2015-130 ICD2015-55 |
A quick-lock all-digital Clock-Data Recovery circuit that does not require a reference clock is propposed. Internal Tim... [more] |
CPM2015-130 ICD2015-55 pp.17-22 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 14:35 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Study on a tolerance for process variability in Single Slope ADC using interpolative TDC Kaihei Hotta, Kenichi Ohhata (Kagishima Univ.) CPM2015-131 ICD2015-56 |
We proposed a novel single slope ADC using an interpolative TDC (ITDC) to develop a high-speed and low-power ADC, and re... [more] | CPM2015-131 ICD2015-56 pp.23-27 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 15:00 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | EMS Evaluation of Adaptively-Tuned Supply-Resonnace Suppression Filter Kohki Taniguchi, Noriyuki Miura, Makoto Nagata (Kobe Univ.) CPM2015-132 ICD2015-57 |
Impedance supply-resonance (SR) of the power distribution network (PDN) is a main cause of EMS vulnerability by self-poi... [more] | CPM2015-132 ICD2015-57 pp.29-32 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 16:20 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Formulation to SAT for Acceleration in 1D Layout Area Minimization of CMOS circuits Hayato Mashiko, Yukihide Kohira (Univ. of Aizu) VLD2015-51 DC2015-47 |
In layout design for LSI circuits, the layout area is minimized to reduce the fabrication cost and to increase the yield... [more] | VLD2015-51 DC2015-47 pp.81-86 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 16:45 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Layout Decomposition into L-Shaped Parts for Variable Shaped-Beam Mask Writer Katsuya Hoshi, Kunihiro Fujiyoshi (TUAT) VLD2015-52 DC2015-48 |
Since electron beam mask writers for LSI mask fabrication can only expose a rectangle shaped-beam, a layout pattern has ... [more] | VLD2015-52 DC2015-48 pp.87-92 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 17:10 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Effective Routing Pattern Generation with an Optimum Tertiary Routing Algorithm for Self-Aligned Quadruple Patterning Takeshi Ihara, Atsushi Takahashi (Tokyo Tech) VLD2015-53 DC2015-49 |
Self-Aligned Quadruple Patterning (SAQP) is an important manufacturing technique for sub 14 nm technology node. Althou... [more] |
VLD2015-53 DC2015-49 pp.93-98 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 17:35 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay and Clock Skew in FPGA Designs Koichi Fujiwara, kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-54 DC2015-50 |
With recent process scaling in FPGAs, interconnection delays and clock skews have a large impact on the latency of a cir... [more] | VLD2015-54 DC2015-50 pp.99-104 |
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