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Technical Committee on VLSI Design Technologies (VLD) (Searched in: 2014)
Search Results: Keywords 'from:2015-03-02 to:2015-03-02'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD | 2015-03-03 16:15 |
Okinawa | Okinawa Seinen Kaikan | [Memorial Lecture]
A Bit-Write Reduction Method based on Error-Correcting Codes for Non-Volatile Memories Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)  VLD2014-173 |
Non-volatile memory is superior to SRAM in terms of its high density and low leakage power but it consumes larger writ... [more] |
VLD2014-173 p.115 |
| VLD | 2015-03-04 08:50 |
Okinawa | Okinawa Seinen Kaikan | Physical Unclonable Function Using RTN-Induced Time-Dependent Frequency Variance in Ring Oscillator Motoki Yoshinaga, Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato (Kyoto Univ.) VLD2014-174 |
(To be available after the conference date) [more] | VLD2014-174 pp.117-122 |
| VLD | 2015-03-04 09:15 |
Okinawa | Okinawa Seinen Kaikan | On PLL Layouts Evaluation based on Transistor-array Style Yuki Miura, Atsushi Nanri, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2014-175 |
The transistor array(TA)-style is a layout methodology where an analog layout is configured on the pattern such that uni... [more] | VLD2014-175 pp.123-128 |
| VLD | 2015-03-04 09:40 |
Okinawa | Okinawa Seinen Kaikan | Ground Bounce Suppressive Effect using Power Switch Driver to control Power Switch Rise Time Tetsutaro Ohnishi, Kimiyoshi Usami (S.I.T.) VLD2014-176 |
While Power Gating technology enables us to reduce leakage current, it causes a serious problem of occurring Ground Boun... [more] | VLD2014-176 pp.129-134 |
| VLD | 2015-03-04 10:20 |
Okinawa | Okinawa Seinen Kaikan | Optimization of sequential circuit in gate-level pipelined self-synchronous circuit design Atsushi Ito, Makoto Ikeda (The Univ. of Tokyo) VLD2014-177 |
With the down-scaling, circuit which has higher robustness is demanded. Dual-pipeline self synchronous circuit have inhe... [more] | VLD2014-177 pp.135-140 |
| VLD | 2015-03-04 10:45 |
Okinawa | Okinawa Seinen Kaikan | LSI implementation of FEC for high-speed optical communication Koji Miyanohana, Susumu Hirano, Hideo Yoshida, Yoshikuni Miyata, Kenya Sugihara, Kazuo Kubo, Yoshiaki Konishi, Kiyoshi Onohara, Noriyuki Minegishi, Takashi Sugihara (Mitsubishi Elec.) VLD2014-178 |
[more] | VLD2014-178 pp.141-146 |
| VLD | 2015-03-04 11:10 |
Okinawa | Okinawa Seinen Kaikan | Energy minimization by voltage choice targeted for logic synthesis in silicon on thin buried oxide Jun Kawasaki, Kimiyoshi Usami (S.I.T.) VLD2014-179 |
Silicon on Thin Buried Oxide (SOTB) technology enables us to reduce supply voltage because the Vth variation can be supp... [more] | VLD2014-179 pp.147-152 |
| VLD | 2015-03-04 11:35 |
Okinawa | Okinawa Seinen Kaikan | A parallel Algorithm for Realizing the Lax-Friedrichs Scheme in Computational Fluid Dynamics and its FPGA Implementation Yusuke Haga, Shinobu Nagayama, Shin'ichi Wakabayashi, Masato Inagi (Hiroshima City Univ.) VLD2014-180 |
In the model of partial differential equations used in complex numerical simulations such as fluid analysis, it is diffi... [more] | VLD2014-180 pp.153-158 |
| VLD | 2015-03-04 13:00 |
Okinawa | Okinawa Seinen Kaikan | An Evaluation of the Performance of a Multiplier in Error-detection/correction-framework Satoshi Ohtsuki, Atsushi Takahashi (Tokyo Tech) VLD2014-181 |
In the current typical of integrated circuits, the performance is determined by the maximum delay between flip-flops. Th... [more] | VLD2014-181 pp.159-164 |
| VLD | 2015-03-04 13:25 |
Okinawa | Okinawa Seinen Kaikan | A Score-Based Hardware-Trojan Identification Method for Gate-Level Netlists Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-182 |
Recently, digital ICs are designed by outside vendors to reduce costs in semiconductor industry. This circumstance intr... [more] |
VLD2014-182 pp.165-170 |
| VLD | 2015-03-04 13:50 |
Okinawa | Okinawa Seinen Kaikan | Implementation and evaluation of architecture using lookup table for approximate computing Shoichiro Sugiyama, tanvir ahmed, Yuko Hara-Azumi (Titech) VLD2014-183 |
Various techniques have been proposed for improving the computation performance so far, where correct computations have ... [more] | VLD2014-183 pp.171-176 |
| VLD | 2015-03-04 14:15 |
Okinawa | Okinawa Seinen Kaikan | List-scheduling for tasks with execution time variation Komei Nomura, Yasuhiro Takashima (Univ. of Kitakyushu) VLD2014-184 |
We propose a list-scheduling for the tasks with execution time variation. The previous scheduling methods use the worst ... [more] | VLD2014-184 pp.177-182 |
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