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Technical Committee on VLSI Design Technologies (VLD)  (Searched in: 2013)

Search Results: Keywords 'from:2014-01-28 to:2014-01-28'

[Go to Official VLD Homepage (Japanese)] 
Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Ascending)
 Results 21 - 33 of 33 [Previous]  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
IPSJ-SLDM, CPSY, RECONF, VLD [detail] 2014-01-29
09:45
Kanagawa Hiyoshi Campus, Keio University An Efficient SIMD Instruction set for Motion Estimation
Ken Miura, Takumi Inomata, Toshio Kondo, Takahiro Sasaki (Mie Univ.)
 [more]
IPSJ-SLDM, CPSY, RECONF, VLD [detail] 2014-01-29
10:25
Kanagawa Hiyoshi Campus, Keio University Implementation of MuCCRA-4: Dynamically Reconfigurable Processor Array
Toru Katagiri, Hideharu Amano (Keio Univ.) VLD2013-122 CPSY2013-93 RECONF2013-76
Although Dynamically Reconfigurable Processor Arrays (DRPAs) are advantageous for embedded devices because of their high... [more] VLD2013-122 CPSY2013-93 RECONF2013-76
pp.119-124
IPSJ-SLDM, CPSY, RECONF, VLD [detail] 2014-01-29
10:50
Kanagawa Hiyoshi Campus, Keio University A configurable switch mechanism for random NoCs
Seiichi Tade, Takahiro Kagami, Ryuta Kawano, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) VLD2013-123 CPSY2013-94 RECONF2013-77
A practical method for making use of the small world phenomenon to increase Network-on-Chips (NoCs)
is proposed. Recent... [more]
VLD2013-123 CPSY2013-94 RECONF2013-77
pp.125-130
IPSJ-SLDM, CPSY, RECONF, VLD [detail] 2014-01-29
11:15
Kanagawa Hiyoshi Campus, Keio University Implementation and Evaluation of Multi-stream Bandwidth Compressor
Tomohiro Ueno, Ryo Ito, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.) VLD2013-124 CPSY2013-95 RECONF2013-78
Bandwidth enhancement with lossless data compression is one of the key solutions to improve performance of custom stream... [more] VLD2013-124 CPSY2013-95 RECONF2013-78
pp.131-136
IPSJ-SLDM, CPSY, RECONF, VLD [detail] 2014-01-29
11:40
Kanagawa Hiyoshi Campus, Keio University Study of accelerator connection using the peripheral bus of OpenMSP430
Ayano Fukuju, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.) VLD2013-125 CPSY2013-96 RECONF2013-79
This paper reports evaluating relationship between several transfer methods and application processing time for the syst... [more] VLD2013-125 CPSY2013-96 RECONF2013-79
pp.137-142
IPSJ-SLDM, CPSY, RECONF, VLD [detail] 2014-01-29
13:20
Kanagawa Hiyoshi Campus, Keio University A Locality-Driven Task Mapping Algorithm for Multi-FPGA Systems
Hiroki Katano, SeungJu Lee, Nozomu Togawa (Waseda Univ.), Takashi Aoki, Yusuke Sekihara, Mamoru Nakanishi (NTT) VLD2013-126 CPSY2013-97 RECONF2013-80
Recently, a scalable and reconfigurable multi-FPGA system has been
proposed which consists of two or more boards, each ... [more]
VLD2013-126 CPSY2013-97 RECONF2013-80
pp.143-148
IPSJ-SLDM, CPSY, RECONF, VLD [detail] 2014-01-29
13:45
Kanagawa Hiyoshi Campus, Keio University On Boolean Matching of LUT-based Circuits
Yusuke Matsunaga (Kyushu Univ.) VLD2013-127 CPSY2013-98 RECONF2013-81
This paper describes two speed-up techniques for Boolean matching of
LUT-based circuits.
One is one-hot encoding tec... [more]
VLD2013-127 CPSY2013-98 RECONF2013-81
pp.149-154
IPSJ-SLDM, CPSY, RECONF, VLD [detail] 2014-01-29
14:10
Kanagawa Hiyoshi Campus, Keio University Dynamic Operation Binding in Distributed Controller for Supporting Functional Units with Variable Latency
Shinji Yamashita, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2013-128 CPSY2013-99 RECONF2013-82
This article presents a new distributed method for controlling circuits with variable latency units, which can dynamical... [more] VLD2013-128 CPSY2013-99 RECONF2013-82
pp.155-160
IPSJ-SLDM, CPSY, RECONF, VLD [detail] 2014-01-29
14:50
Kanagawa Hiyoshi Campus, Keio University Prediction Model for Process Variation and BTI-Induced Degradation by Measurement Data on FPGA
Michitarou Yabuuchi, Kazutoshi Kobayashi (Kyoto Inst. of Tech.) VLD2013-129 CPSY2013-100 RECONF2013-83
We propose a prediction model for BTI-induced degradation by
measurement data on 65nm-process FPGAs. BTI-induced degrad... [more]
VLD2013-129 CPSY2013-100 RECONF2013-83
pp.161-166
IPSJ-SLDM, CPSY, RECONF, VLD [detail] 2014-01-29
15:15
Kanagawa Hiyoshi Campus, Keio University A Reduction Method of Writing Operations to Non-volatile Memory by Keeping Data Difference for Low-Power Circuit Design
Hiroyuki Shinohara, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) VLD2013-130 CPSY2013-101 RECONF2013-84
In order to reduce the power consumption of LSI,
unnecessary parts should be powered off with fine granularity,
and c... [more]
VLD2013-130 CPSY2013-101 RECONF2013-84
pp.167-172
IPSJ-SLDM, CPSY, RECONF, VLD [detail] 2014-01-29
15:40
Kanagawa Hiyoshi Campus, Keio University Methodology for NBTI measurement using an on-chip leakage monitor circuit
Takaaki Sato, Kimiyoshi Usami (Shibaura Inst. of Tech.) VLD2013-131 CPSY2013-102 RECONF2013-85
Miniaturization in recent years ,LSI's aging has become prominent as a factor that prevents the normal operation.By meas... [more] VLD2013-131 CPSY2013-102 RECONF2013-85
pp.173-178
IPSJ-SLDM, CPSY, RECONF, VLD [detail] 2014-01-29
16:20
Kanagawa Hiyoshi Campus, Keio University PerCUDA: CUDA Binding Framework for Perl
Takayuki Fukumoto, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2013-132 CPSY2013-103 RECONF2013-86
This article presents ``PerCUDA,'' which is a framework of GPGPU by way of script language Perl.
In PerCUDA, kernel fun... [more]
VLD2013-132 CPSY2013-103 RECONF2013-86
pp.179-184
IPSJ-SLDM, CPSY, RECONF, VLD [detail] 2014-01-29
16:45
Kanagawa Hiyoshi Campus, Keio University Binary Synthesis of Hardware Accelerator Tightly Coupled with CPU
Shimpei Tamura, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Kanbara (ASTEM), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2013-133 CPSY2013-104 RECONF2013-87
This article presents a method of synthesizing hardware that accelerates specified sections of binary programs. The acce... [more] VLD2013-133 CPSY2013-104 RECONF2013-87
pp.185-190
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